Gaps In The Verification Flow

By Brian Bailey - 25 Oct, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss the state of the functional verification flow with Stephen Bailey, director of emerging companies at [getentity id="22017" e_name="Mentor Graphics"]; [getperson id="11079" comment="Anupam Bakshi"], CEO of [getentity id="22168" e_name="Agnisys"]; [getperson id="11124" comment="Mike Bartley"], CEO of [getentity id="22868" e_name="Test and Verification... » read more

2.5D Surprises And Alternatives

By Ed Sperling - 20 Oct, 2016 - Comments: 0

Semiconductor Engineering sat to discuss advanced packaging issues with Juan Rey, senior director of engineering for Calibre at [getentity id="22017" e_name="Mentor Graphics"]; Max Min, senior technical manager at [getentity id="22865" e_name="Samsung"]; and Lisa Minwell, [getentity id="22242" e_name="eSilicon's"] senior director of IP marketing. What follows are excerpts of that conversation. ... » read more

What Can Go Wrong In Automotive

By Ed Sperling - 06 Oct, 2016 - Comments: 1

Semiconductor Engineering sat down to discuss automotive engineering with Jinesh Jain, supervisor for advanced architectures in Ford’s Research and Innovation Center in Palo Alto; Raed Shatara, market development for automotive infotainment at [getentity id="22331" comment="STMicroelectronics"]; Joe Hupcey, verification product technologist at [getentity id="22017" e_name="Mentor Graphics"]; ... » read more

Gaps In The Verification Flow

By Brian Bailey - 29 Sep, 2016 - Comments: 0

Stacked Die Changes

By Ed Sperling - 21 Sep, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss advanced packaging with David Pan, associate professor in the department of electrical and computer engineering at the University of Texas; Max Min, senior technical manager at [getentity id="22865" e_name="Samsung"]; John Hunt, senior director of engineering at ASE; and Sitaram Arkalgud, vice president of 3D portfolio and technologies at Invensas. ... » read more

Stacked Die Changes

By Ed Sperling - 15 Sep, 2016 - Comments: 1

Cars, Security, and HW/SW Co-Design

By Jeff Dorsch - 13 Sep, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss parallel hardware/software design with Johannes Stahl, director of product marketing, prototyping and FPGA, [getentity id="22035" e_name="Synopsys"]; [getperson id="11411" comment="Bill Neifert"], director of models technology, [getentity id="22186" comment="ARM"]; Hemant Kumar, director of ASIC design, Nvidia; and Scott Constable, senior member of ... » read more

Optimization Challenges For 10nm And 7nm

By Brian Bailey - 06 Sep, 2016 - Comments: 0

Optimization used to be a simple timing against area tradeoff but not anymore. As we go to each new node, the tradeoffs become more complicated involving additional aspects of the design that used to be dealt with in isolation. Semiconductor Engineering sat down to discuss these issues with Krishna Balachandran, director of product management for low-power products at [getentity id="22032" e... » read more

What’s Important For IoT—Power, Performance Or Integration?

By Ed Sperling - 01 Sep, 2016 - Comments: 0

Semiconductor Engineering sat down with Steve Hardin, director of product development for AT&T's IoT Solutions Group; Wayne Dai, CEO of VeriSilicon; John Koeter, vice president of the Solutions Group at [getentity id="22035" e_name="Synopsys"]; and Rajeev Rajan, vice president for IoT at [getentity id="22819" comment="GlobalFoundries"]. What follows are excerpts of that conversation. To vie... » read more

Cars, Security, And HW-SW Co-Design

By Jeff Dorsch - 31 Aug, 2016 - Comments: 0

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Knowledge Centers
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category: Round Tables

category: IoT, Security & Automotive

Gaps In The Verification Flow

2.5D Surprises And Alternatives

What Can Go Wrong In Automotive

Gaps In The Verification Flow

Stacked Die Changes

Stacked Die Changes

Cars, Security, and HW/SW Co-Design

Optimization Challenges For 10nm And 7nm

What’s Important For IoT—Power, Performance Or Integration?

Cars, Security, And HW-SW Co-Design