Stacked Die Changes

Experts at the table, part 3: How mature are high-speed interconnects and what hurdles remain for widespread adoption.


Semiconductor Engineering sat down to discuss advanced packaging with David Pan, associate professor in the department of electrical and computer engineering at the University of Texas; Max Min, senior technical manager at Samsung; John Hunt, senior director of engineering at ASE; and Sitaram Arkalgud, vice president of 3D portfolio and technologies at Invensas. What follows are excerpts of that conversation. To view part one, click here. Part two is here.

SE: With thin wires there are issues with RC delay, while with advanced packaging there are alternatives such as interposers. But are these new interconnects ready for volume production, or are we will in learning mode?

Hunt: We don’t know everything there is to know. It’s still evolving. Cost is the big issue, so we’ve developed some partnerships to lower the cost for 2.5D interposers with TSVsXilinx has come out with a chip that doesn’t use TSVs, so it cuts out a lot of the cost structure. We are working to develop a similar product that doesn’t use exactly the same structure. Hopefully all of them will offer a lower cost solution. The problems that exist with them are warpage. Putting a mold compound on the back of silicon leads to warpage. That’s the issue. We’re still on learning curves here. The challenge all of us are dealing with is not just about making a final package, but to be able to develop one for high-volume production. We are working on high-yields and low cost so that it is accepted by the industry. Trying to get high-90% yield like AMD’s Fuji product is a challenge. TSMC is still working on yield issues with its InFO fan-out. Everyone is trying to get it manufacturable at a reasonable cost. These are very complex structures. All of the packaging is becoming much more complex. But it’s also tying in multiple disciplines. We’re using different processes. We gained knowledge on the die-to-wafer bonding on the interposer to use in fan-out solutions. So you are continuing evolving new technologies, not just from a structure or process perspective. That’s going to benefit everyone.

SE: How much of this is dependent on the design of the chip versus the back-end manufacturing?

Hunt: From a packaging perspective, it’s becoming much more obvious that we need co-design if you want to have a cost-effective, manufacturable solution. For one of our largest customers, the biggest concern on the packaging side is that their design guys won’t listen to them. The design guys are doing things the way they’ve always done it without taking into consideration changes that have to be made to make it manufacturable from a packaging perspective. That is becoming more and more necessary. Before it was a luxury that was nice to have, because it typically was just thrown over the wall for packaging. You can still do that, but you won’t end up with a cost-effective solution.

Pan: But if you’re packaging, does that mean you have design rules for the circuit design? Without you giving feedback to the designers, it’s difficult.

Min: For chip-package co-design, if the chip designer has a problem like I/O, it may affect the pad or bump position. And later on, the package can affect how those signals go out. So the package guys go back to the designers and ask if they can do something different, and the answer is no because they don’t have a solution. The chip designers and package designers then have to sit down together and come up with a reasonable functional map, then do the simulation. So while these people do the simulation, they also need to define the structure itself. For 2.5D, it may be about an interconnect. If you have very high resistance, the high-speed interconnect may not work. They still need to talk about bump pitch, line spacing and how many layers there are on a silicon interposer. So the designer and the simulation guys have to sit down and figure out how to make it work. Then, based on that, you can talk about design rules. Those design rules are actually manufacturing rules rather than rules for design. They are slightly different. There may be some modification required. So you may need 2 microns instead of 2.1 microns. A lot of packaging substrate manufacturers are investing a lot of money in new materials, new copper, and things like that to make this work.

Hunt: There is more and more cooperation between design tools that are available to integrate at different levels of assembly. But if you look at Intel’s EMIB, all of the interconnect between die has to be on the edge. It has to be specifically designed for that package. One of our fan-out customers designed a die for a specific fan-out solution. You can’t use another fan-out solution because it’s designed for the characteristics of that structure. So it’s becoming more and more critical to work together on the design—the substrate, package and the design.

Arkalgud: You cannot design in isolation and throw it over the wall. If it falls apart, then the front end designers never want to do it again. There is no way out of it. But back to something we were talking about earlier, if you look out over the past few years there were questions about whether we need interposers because they cost too much. Now, the mindset is that for certain applications it makes sense. We are beyond the question about whether we need to use interposers. So then it turns into a discussion about what types of interposers we need. Glass has always been there, but not quite making it. Silicon makes a lot of sense, although it’s expensive. Cost always is a question. But with more functionality and demand for less power, that is defining new areas.

Hunt: No package is a universal solution. It’s defined by the end application. Certain packages are more suitable for certain structures and applications. You have to work with the customer to understand requirements for a package before you define that package, whether it’s TSVs, fan-out, wire-bond or solder balls.

Min: A lot of customers are talking about advanced packaging and conventional packaging. They want to understand where we are with package structure.

Related Stories
Stacked Die Changes Part 1
There are new and better options for packaging chips together as the semiconductor industry begins to figure out what works and what doesn’t.
Stacked Die Changes Part 2
Different coefficients of thermal expansion cause warpage problems; known good die issues.
Tech Talk: 14nm And Stacked Die
Why the 14nm node will be long lived, and how it will be used in 2.5D and 3D-IC packages.

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