Stacked Die Changes

Experts at the table, part 2: Different coefficients of thermal expansion cause warpage problems; known good die issues.


Semiconductor Engineering sat down to discuss advanced packaging with David Pan, associate professor in the department of electrical and computer engineering at the University of Texas; Max Min, senior technical manager at Samsung; John Hunt, senior director of engineering at ASE; and Sitaram Arkalgud, vice president of 3D portfolio and technologies at Invensas. What follows are excerpts of that conversation. To view part one, click here.

SE: Any surprises when you package chips together in multiple configurations?

Hunt: With chip-package interaction, that’s critical for the design of the silicon. But we get silicon from the fabs, and all of the silicon does not respond the same. Sometimes we have to tailor the package to the silicon from a particular foundry. They don’t all perform the same, so you can’t put dies from different foundries in the same package and expect them to perform the same.

Min: We are moving from big structures to ultra-fine structures as we move to 7nm. So we will have more and more functions and I/Os in a small area. Because of that we may need different interconnects—solder balls, microbumps, copper pillars and now copper-to-copper joints. Maybe later on someone will develop something without copper to integrate in a package. The TSV is one kind. A via where you plate the hole is a key technology invented years ago. Now people are talking about microvias, solder balls, double wire bonding and copper pillars. But now people are trying to eliminate the solder from the pillars, and completely remove the bumping structures and interconnects from the package. There is a lot of innovation to support end customer requirements. The end customer would like to integrate the system on a board. And you can use existing technologies. But now people are looking for package solutions of a given size. Some people care about the ‘x,y’ dimensions, some people care about the ‘z’ height. If you don’t talk about the z height but use wirebonding, they’re likely to use a short interconnect. The end customer will tell us what to do.

SE: One of the complaints about 2.5D is that as one substrate expands at a different rate than another substrate, the stress is put on the corner balls. It was beginning to rip the substrate off the balls and crack the balls. It sounds as if you’ve solved some of that, right?

Min: There are some solutions—copper CTE (coefficient of thermal expansion) versus silicon CTE and organic substrates are different. When you put them together, even if you have silicon substrates and silicon interposers, there are different CTEs in a package. At the end of the day you may have an open or short here and there. Sometimes at the center of the package it cannot be connected to the board. Those problems are already out there. We have to analyze it before we build it. You don’t want to build a package without simulation. That has to be thermal and mechanical. We have to use all kinds of simulation software to find out if any technique will cause problems.

Hunt: Every time you go to an RDL (redistribution layer) or sputtering or curing cycle, you change the warpage of the material. Not only are you modeling for the end product in terms of how much warpage can you get, but you have to be able to process it in the first place. With the CTE mismatches, we’re making some progress. There are more and more substrates that have very low CTEs. But then they have to connect to a board that has a high CTE. One thing that fan-out has going for it is that you can take CTE fan-out mold compounds. The corner balls in a fan-out are usually in the mold compound, not in the silicon, so you’re not putting the stress on the silicon. The CTE of that mold compound is in between the silicon, which is around 3, and the board, which is somewhere around 17. It gives you some buffering. We’ve come up with different schemes to mediate the CTE mismatch issues and to make it more robust from a reliability standpoint. It’s still definitely a problem, though, with smiling and crying (warpage direction). If it smiles too much, you cry.

Arkalgud: It also depends on the size of the die. Smaller die sizes can be more accommodating. But you still need to model as accurately as you can, not only the end product but also the processes. Then you just keep validating it over and over again.

Hunt: We’re still on learning curves. When we first started with interposers, we were doing the back end of line for those. We were getting CTE mismatches, so we had to modify our nitride mix so we had a balanced construction. You learn these things through experience.

Min: Because of advanced packaging, a lot of the materials guys developed new material. But the new material is never characterized because it has not been used before. So you try to use it and nobody knows how that material will behave chemically or electrically. These are electrically, mechanically and thermally non-linear. So when you try to simulate this you get some results, but when you build it you get different results. It will take some time to make this work.

Hunt: When Infineon came out with a fan-out, the material used for fan-out was a low-temperature polymer. They rushed that to market and it wasn’t fully characterized. Nokia was the only one that would accept it because it had deteriorated so badly that it could not be qualified with any other customer. Everyone had to find another material, and we were very careful to fully characterize it so we did not find ourselves in that situation again.

Min: At the end of the day, the package should be reliable. Otherwise there is no product. Everyone has to do as early engineering as possible so we can use that technology. We don’t want to have to go back again and again. One customer changed the design to solve the problem, but that takes time.

SE: We’ve been hearing for a while about organic interposers. Are they ready for mass-market adoption?

Hunt: We’re building a chip-last solution, which is basically organic 2.1, where we build up an RDL pattern on a carrier wafer and then do a flip-chip assembly and surface mount on that. That’s essentially a 2.1 organic substrate. It’s not in volume production yet but it is in qualification stages.

SE: What’s the difference between 2.5? and 2.1D?

Hunt: 2.5D is typically used to describe a silicon or glass interposer. 2.1D is a tag for an organic version of that.

Min: Silicon interposers are out there. In between 2.5D and 2.1D there is another technology, which is RDL on a WLP. That looks like a feasible solution for a product. Everyone is talking about it now. It looks okay to go. But silicon interposer plus WLP has some problems with known good die. With WLP, you may have a good die, but once you mold it and go to RDL, you don’t know which known good die has gone bad. All you know is that you start with known good dies, but when you package and add the interconnect, then somehow the system doesn’t work and no one knows why. So after that the end customer wants conventional packaging where you assemble it on a substrate and let it go. That is 2.1D packing substrate or interposer. The concept is very simple. The foundation is a package substrate, and on top of that you add the interconnect. Once you have a 2 micron space, you can have 2.5D. That’s why a lot of substrate makers are working on 2.1D substrates.

Pan: We have done some 3D modeling for testing mechanical stress. In terms of research, there is some active research on monolithic 3D. That is quite far ahead. We are making good progress there. That is one direction. 3D hasn’t caught on as fast as expected, though, because 3D (finFET) scaling is still continuing. In 2010, there were a lot of citations about TSV research. That was around 32/28nm. We now have 22nm, 14nm, and it appears that 10 and 7nm will happen. Ultimately, though, whether it’s 5nm or 3nm, it will stop in terms of horizontal scaling. Demand for heterogeneous integration will be in great demand. At that point, when we have real volume production with DFM and research about reliability, then it will be a different story.

Related Stories
Stacked Die Changes Part 1
There are new and better options for packaging chips together as the semiconductor industry begins to figure out what works and what doesn’t.
Stacked Die Changes Part 3
How mature are high-speed interconnects and what hurdles remain for widespread adoption.
Tech Talk: 2.5D Issues
How ready is this packaging approach and what problems remain?
Advanced Packaging Options, Issues
New fan-out technology under development; 2.5D trouble spots come into focus.
2.5D Becomes A Reality
Experts at the table, part 1: Lower power, better bandwidth and smaller form factor propel advanced packaging into commercial use; cost is still rather murky.


Dev Gupta says:

All that excitement about 3d and even 2.5d happened as non Packaging people got interested in Packaging. There are several cardinal rules in Packaging ( “do no harm”, stress, warpage, must cost less than the chips, .. ) that will gradually sink in and even after heterogeneous integration becomes a must the final split will be dominated by 2.1 d with chip last. BTW even for performance ( e,g. memory bandwidth ) driven applications there are elegant electrical solutions that do not require the “Popular Mechanics” ( i,e. TSV based die stack ) approach.

Leave a Reply

(Note: This name will be displayed publicly)