Stacked Die Changes

Experts at the table, part 1: There are new and better options for packaging chips together as the semiconductor industry begins to figure out what works and what doesn’t.


Semiconductor Engineering sat down to discuss advanced packaging with David Pan, associate professor in the department of electrical and computer engineering at the University of Texas; Max Min, senior technical manager at Samsung; John Hunt, senior director of engineering at ASE; and Sitaram Arkalgud, vice president of 3D portfolio and technologies at Invensas. What follows are excerpts of that conversation.

SE: We’ve been hearing a lot about 2.5D, 2.1D and fan-outs. Where are we with advanced packaging and stacking die and putting things on boards? What is the state of the industry?

Pan: There are a lot of notions about 3D. There is monolithic 3D, TSV-based 3D, 2.5D, and transistor structures in 3D. At 16/14nm, 10nm, and 7nm, there are finFETs . Those are 3D, too. There also is 3D NAND flash. There was a lot of research happening in 2010 on TSVs, but six years later we still haven’t seen microprocessors with a full stack of memory. There are many challenges for 3D, including thermal and thermo-mechanical stress. From a design perspective, you can model them, but ultimately it still boils down to cost and the killer applications. TSV-based works for memory, but for heterogeneous integration is still is not happening yet. That’s why people are moving more toward interposers and 2.5D packaging.

Min: For many years, people were talking about integration on-chip. Now they are talking about integration in a package. Now they’re jumping into 3D stacking, not just 2.5D, as a product.

Hunt: Last year we came out with the first HBM and processors with AMD in the Fuji product. That used actual TSVs. But we also gained a lot of experience in doing that, including die-to-wafer bonding capabilities. At the same time, we’ve been developing fan-out solutions. We have multiple options for fan-out. We used to look at the fan-out, which has a capability now of about a 2-micron line and space, as a poor man’s TSV or interposer. We came out with a high-density fan-out in January, which is a 16nm and 28nm die side-by-side fan-out, but instead of being a package with balls it has bumps on it. It’s then treated as if it’s a die, and then placed on a BGA substrate. It’s a hybrid solution. But using the fan-out eliminates the need to use a TSV interposer. There are alternatives, depending on the complexity of the product. That one has more than 1,000 interconnects between metal layers. But we have lower-cost solutions. We use TSVs in the interposers, but we also use TSVs as via last for MEMS applications. So there are a lot of MEMS accelerometers that need through-interconnects to reduce the XY dimensions of the package. We use TSVs there. It’s not an interposer solution. For the fan-out we have multiple means of getting through the package. Some are plated up interconnects. Some are TSV dies inserted into the mold compound. You can laser drill, but we don’t choose to do that. We actually have 12 different variations of fan-out in various stages of engineering and development. Some offer 2D solutions, some offer 3D solutions. But we see more and more of our customers moving up the food chain from single-die solutions to multiple die solutions and system-in-package solutions where they have to integrate multiple die in a package. Some of those require 3D, some do not. Some can be done side by side. Fan-out has been the buzzword for the past six months, and everyone wants to kick the tires on it and see what it can and can’t do. It can do a fair amount, but it can’t do the same density today as silicon interposers, so we have multiple solutions in the packaging industry. All of the OSATs are entering the race and trying to achieve the same goals, because all of our customers want two or three suppliers and multiple solutions.

Arkalgud: We’re working on 3D stacking. When you are stacking chips together you are dealing with thin dies, and you have a vertical interconnect of some kind. There is a through-silicon via or a wire bond or an optical connection. A lot of this industry has been focused on high-performance CMOS. But if you look at image sensors, that satisfies all of these criteria. There are through-silicon vias. There are logic die in cameras that are below the sensors. And these are very, very thin die. It’s in very high volume production and it’s also very cheap. 3D is happening in a very big way, but in a different area than we typically look at. If you look at high-performance CMOS, the AMD product is a perfect example of what’s being done. Before that you had the Xilinx FPGA that sold for $10,000 a part. This is going to sell for less than $1,000, and it has four HBM stacks, it has a massive interposer with through-silicon vias, and it’s happening. MEMS is another area. It is taking place. Several years ago, there were some pretty horrible pictures about using TSVs and the dies cracking. Nobody thinks about that anymore. With 3D, you need a vertical interconnect of some kind, and depending upon what you need and how many I/Os, you can do it with TSVs or wirebonds or something else.

SE: There has been a lot of talk about known good die, where if you put two good die together they may not work the way they did individually. Has the industry made progress on this?

Hunt: We’ve been calling them probably good die.

SE: Is there still the same kind of momentum for stacking die as there was before we knew there would definitely be a 7nm process node?

Arkalgud: There’s even more of a requirement. For certain applications, you do need the benefits of shrinking—although that’s becoming more of a question now. It’s not a cost-effective solution. But as you get into more and more functionality requirements, you don’t need the leading-edge technology. If you’re doing a 2D SoC, your whole die is held hostage to whatever your smallest node is. 3D allows you to break it out.

Hunt: Yes, we’re seeing more and more partitioning, where the digital functions are going into the advanced nodes and the analog and RF are staying in the older nodes because it’s a lower-cost solution. One thing you have to think about is why you want TSVs. A lot of times it’s the interconnect between die. It doesn’t have to be done vertically. It can be done horizontally, depending on whether you want a thin package or a small X and Y. The real key is to interconnect those die. Things like the slim products that are TSV-less but still use front-end fab capability, you can do it horizontally. Intel’s EMIB is a horizontal interconnect for high-density integration of die. The interconnect is determined by how you want to configure your package.

Arkalgud: As long as you have two dies on top of each other, you don’t really have to have a TSV. You could do horizontal interconnects. But if you go above two, you have to have a vertical interconnect.

SE: Have we gotten to the point where we have wafer-level bonding?

Hunt: The Fuji from AMD is done on a wafer. The interposers are on a wafer. They’re doing die-to-wafer bonding on a wafer. On-chip, on-substrate, it’s all die-to-wafer bonding. The underfill is put on in wafer form, and everything is done in wafer form. We’re already doing 3D packages and interconnect assemblies on a wafer.

SE: There has been a lot of concern about the coefficient of thermal expansion (CTE) for underfill not being the same from one layer to the next. How do we solve that problem?

Arkalgud: We believe that direct bonding, whether it is offset or hybrid bonding, makes perfect sense going forward. You end up with a very complex system otherwise. You have microbumps that don’t scale too well, and you also have two layers with thermally mismatched underfill and also probably organic layers in between. There are more and more thermo-mechanical issues, especially if you have very large die. But if you could eliminate all of that and just have a silicon-to-silicon bond with copper-to-copper interconnects, that is a very clean way to go about that. We’re seeing that in image sensors. The latest Sony image sensor uses DBI, or direct-bond interconnect. That’s in volume manufacturing. That makes a lot of sense for many applications, whether it’s MEMS or 2.5D.

Hunt: Eventually you have to connect that silicon to a substrate. At that point you still need underfill.

Arkalgud: There isn’t a silver bullet out there.

Hunt: The underfills are advancing, as well. We did a package-on-package, which is three different levels of mold compound or underfill, and they span orders of magnitude difference in particle filler size. As we do the mold only underfill (whereas we used to do capillary underfill), we use finer and finer filler particles. So our filler particles are nanospheres. They can fill very small space. That changes the CTE of that material. People are starting to adapt the underfill to the application. At that point you have to take into account the CTEs.

Pan: Thermo-mechanical stress is a problem. We have worked on TSV-based as well as microbumps and packaging. There is indeed a lot of mismatch between the thermal coefficient and the microbumps. That can affect the underlying structure and the stress and the mobility. We have published some papers on this. There is also a lot on the material side—how to use different materials.

Related Stores
Stacked Die Changes Part 2
Different coefficients of thermal expansion cause warpage problems; known good die issues.
Stacked Die Changes Part 3
How mature are high-speed interconnects and what hurdles remain for widespread adoption.
Tech Talk: 14nm And Stacked Die
Why the 14nm node will be long lived, and how it will be used in 2.5D and 3D-IC packages.
Will 3D-IC Work?
The jury is still out about just how widespread this packaging approach will become.
Tech Talk: 2.5D Issues
How ready is this packaging approach and what problems remain?

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