2.5D Becomes A Reality

Experts at the table, part 1: Lower power, better bandwidth and smaller form factor propel advanced packaging into commercial use; cost is still rather murky.


Semiconductor Engineering sat down to discuss 2.5D and advanced packaging with Max Min, senior technical manager at Samsung; Rob Aitken, an ARM fellow; John Shin, vice president at Marvell; Bill Isaacson, director of ASIC marketing at eSilicon; Frank Ferro, senior director of product management for memory and interface IP at Rambus; and Brandon Wang, engineering group director at Cadence. What follows are excerpts of that conversation.

SE: Where is 2.5D and what problems remain?

Aitken: 2.5D has moved from ‘when’ and ‘if’ to ‘how.’ It’s happening all over the place. It’s interesting to look at the progress from five years ago, when everyone thought we’d be doing TSV-based 3D. Then people started that and realized it was harder and more expensive than they thought. Then we went to 2.5D with interposers. They worked well for some applications, but they’re too expensive for others. Now there are alternate solutions of fan-out packaging or direct bonding on PCB, which is kind of like 2.5D, or Intel embedded silicon channels. What we’ll see in the short term will be even more options as people try new things. Then we’ll hit a few of them that are great and we will focus on them.

Isaacson: We’ve seen HBM adoption really driving 2.5D. We’ve gone from customers interested in what that might be to engaging in production programs. The question for us is how that expands into other applications—maybe repetitious designs, or chopping that up, or similar designs. We’re definitely seeing customer interest in that sort of scenario and we’re trying to figure out how to convert that from an interesting idea to production reality.

Shin: 2.5D is a more plausible solution for semiconductor technology issues going forward, and we see a lot of applications that will take advantage of 2.5D technology. They are the ones that need to make faster connections between chips.

Wang: This year, InFO and InFO-like fan-outs and packaging are a hot topic. That does have wider coverage in terms of applications. It’s MEMs-based integration. In addition, true 3D is happening with TSV-less die integration. That also covers one of the areas with no package, which is die-on-PCB, an approach that gets rid of the traditional BGA substrate. Those are the trends moving forward. These are at least even in cost with traditional packaging, but with reduced parasitics in PCB-less die integration. You get the performance at the same time without really increasing the cost. The cost is where this all gets dicey because it depends on which point you pick when you do cost comparisons. You can always look at cost different ways, and for heterogeneous integration it’s still early. We’ll see a clear cost comparison when these packages are heading toward the production phase with sufficient volumes and economies of scale. The challenge when we move to a fan-out is that the variation of these technologies gets pretty big. So with OSATs, they all have their own recipes and all sorts of packaging technology. That is where you will see a lot of name confusion, which will make cost comparisons a challenge.

Min: People talked a lot about package-to-package connections. Now they’re moving to chip-to-chip connections. There are a lot of technical challenges and non-technical challenges, such as yield and cost. But there is a lot of new technology coming in for 2.5D.

Ferro: For 2.5D to work, there has to be enough of a need from customers to overcome the additional engineering costs associated with it. Back in the mobile days when we started seeing 3D packaging, it was because we needed space. We needed to get more memory into a smaller footprint. I worked for a multi-chip module company for a while doing WiFi and Bluetooth modules. There had to be a clear economic advantage to use that. Today we’re seeing bandwidth as a driver in the case of HBM. There’s a need to create another tier in the hierarchy, so customers are interested in looking at the cost tradeoffs of 2.5D using silicon interposer, and HBM versus traditional DRAM. Are the economics there? For the people who really want it and need it, yes. For the masses, we still have a way to go. From a power and performance standpoint, Wide I/O was really nice. But when one of the big players exited the mobile phone market, there was no longer a big driver to work out the manufacturing issues.

SE: We’ve seen it show up so far in cost-insensitive markets such as networking and servers. Is cost still a barrier to entry? Or are the technology drivers sufficient to make that less of an issue?

Aitken: It’s a combination of bandwidth plus energy or power. Cost fits in there, as well. So how do you get the most bandwidth with a minimal energy budget and at the same time having a manageable cost budget? That’s why we’re seeing this disparity in solutions. Some of them are emphasizing cost, some are emphasizing bandwidth, other are emphasizing energy. It’s where they’re sitting in that spectrum that’s driving this plethora of solutions.

Isaacson: It’s customers in the networking and high performance compute spaces. What’s driving them is memory bandwidth. They don’t have any other good solution today other than HBM. You need 40 DDR cores to get 1 HBM module. These are relatively cost-insensitive customers, but they still care about cost.

Aitken: But there’s also providing that bandwidth that has to be considered when you talk about cost. GPUs and CPUs can suck up immense amounts of bandwidth very quickly. Unless there’s some way of feeding them, then the amount you spend on the processing capability isn’t fully utilized.

Ferro: Power is important. If you look at HMC (Hybrid Memory Cube), it was really hot two years ago, but it has fizzled since then. By serializing all those signals you need high-speed SerDes. And then you have to look at the power of high-speed SerDes, versus HBM, which is wide and relatively slow. Power in HMC might have been less complex when seen from a 2D to 3D evolution standpoint because it was similar, but HBM won out because of lower power and lower complexity.

Isaacson: If you take away interposers, everything about it is better. It’s lower power, multi-sourced, and it’s an open standard. The scary part, which was the interposer, has now been solved.

Wang: Interposer is an additional cost. One thing we haven’t mentioned here is the form factor. Mobile is still driven by form factor. High-performance computing does not have enough volume to drive innovation. If you look at who is playing in the mobile space, you can name a few guys. If you look all the packaging options, whether they’re chip first or chip last, the big change is the ability to move beyond the X and Y axes into the Z direction. That is good for mobile. But you do need to reduce the height with the memory and the IC size, which is why fan-out is so popular.

Aitken: But you could conceive of a low-volume solution that isn’t as efficient as fan-out packaging. Form factor is important, but I would argue that bandwidth and energy are just as important in mobile-land.

Wang: It is. But if you look at watches, the form factor becomes even more critical. If you look at a newly emerged categories like wearables, it’s still pretty loose in terms of cost and design, so you have a little space. Once that gets incorporated into the mobile market well enough, people will start thinking about why regular mobile devices can’t take advantage of that kind of packaging. The total package is much smaller.

Min: Making it smaller helps to reduce cost, too. And higher performance will make a better system. We can adopt that technology. Some day it will be mature enough so that anyone can use it. We already know how to use silicon interposers for memory, but more and more will be added onto this technology so that it goes well beyond just memory. So we may see IP and sensors connected with this. People will pull this all inside a package. We see it for high-performance and mobile systems. In parallel, we are developing a lot of technologies so that we can adopt those technologies and make products when the market is ready.

SE: What was the driver behind Marvell’s push into this kind of packaging approach?

Shin: We really care about performance and we care about cost, because that’s still important to our customers, so we developed a new architecture (MoChi) with very high bandwidth. These all require advanced packaging technologies. We are looking at this for high-end systems all the way to low-end systems. At the high end, we can move up the performance and still keep the costs down. At the low end, we can add more bandwidth while focusing on the cost. We need to cover the entire spectrum with this packaging technology. If one guy jumps in, others will follow and the costs will go down everywhere.

Related Stories
2.5D Becomes A Reality Part 2
How Many Cores?
Thinking Outside The Chip
IP To Meet 2.5D Requirements
Improving Yield Of 2.5D Designs


Dev Gupta says:

this “expert” discussion on Heterogeneous Integration by Adv. Packaging is INCOMPLETE w/o a few actual experts in Packaging / Interconnects !

Ed Sperling says:

Hi Dev, We’ve done a number of stories in this area and have discussed interconnects in the past–everything from interposers and TSVs to silicon photonics to silicon bridges. We’ve got a fair amount of information about this in our Knowledge Center, as well. But there are only so many people we can fit at one table at the same time and still have a reasonable discussion. This is an ongoing issue, and we will have more roundtables as well as in-depth, multi-sourced stories.

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