category: System-Level Design

category: IoT, Security & Automotive

The Perfect Risk
By Brian Bailey - 27 Sep, 2018 - Comments: 0

The development of semiconductors is an act of risk management. Very simply put, if you take on too much risk, it could lead to product failure or a missed market window, both of which can cost $M. For a company that only produces one or two products a year, that can spell total disaster. If you do not take on enough risk, you are probably not going to end up with a competitive product that ... » read more

A Paradigm Shift With Vertical Nanowire FETs For 5nm And Beyond
By Taigon Song - 27 Sep, 2018 - Comments: 1

When I was in undergrad not so long ago, all my circuits and semiconductor textbooks/professors were talking about MOSFETs (metal-oxide semiconductor field-effect transistor) that were just “better” than BJTs (bi-polar junction transistor). There were still some old professors talking about how they did an excellent job using BJTs, but everyone knew it was MOSFET that was leading the game i... » read more

Next-Generation Liberty Verification And Debugging
By WeiLii Tan - 27 Sep, 2018 - Comments: 1

Accurate library characterization is a crucial step for modern chip design and verification. For full-chip designs with billions of transistors, timing sign-off through simulation is unfeasible due to run-time and memory constraints. Instead, a scalable methodology using static timing analysis (STA) is required. This methodology uses the Liberty file to encapsulate library characteristics such ... » read more

AI Chips Must Get The Floating-Point Math Right
By Sergio Marchese - 27 Sep, 2018 - Comments: 0

Most AI chips and hardware accelerators that power machine learning (ML) and deep learning (DL) applications include floating-point units (FPUs). Algorithms used in neural networks today are often based on operations that use multiplication and addition of floating-point values, which subsequently need to be scaled to different sizes and for different needs. Modern FPGAs such as Intel Arria-10 ... » read more

Is Cloud Computing Suitable for Chip Design?
By Brian Bailey - 27 Sep, 2018 - Comments: 2

Is semiconductor design being left behind in a cloud-dominated world? Finance, CRM, office applications and many other sectors have made the switch to a cloud-based computing environment, but the EDA industry and its users have hardly started the migration. Are EDA needs and concerns that different from everyone else? We are starting to see announcements from EDA companies, but few cheerleaders... » read more

The Revenge Of The Digital Twins
By Frank Schirrmeister - 27 Sep, 2018 - Comments: 0

How do we verify artificial intelligence? Even before “smart digital twins” get as advanced as shown in science fiction shows, making sure they are “on our side” and don’t “go rogue” will become a true verification problem. There are some immediate tasks the industry is working on—like functional safety and security—but new verification challenges loom on the horizon. As in pr... » read more

Betting Big On Discontinuity
By Ed Sperling - 27 Sep, 2018 - Comments: 0

Wally Rhines, president and CEO of Mentor, a Siemens Business, sat down with Semiconductor Engineering to talk about the booming chip industry, what's driving it, how long it will last and what changes are ahead in EDA and chip architectures. What follows are excerpts of that conversation. SE: The EDA and semiconductor industries are doing well right now. What's driving that growth? Rhine... » read more

Giving Cars A Bird’s-Eye View
By Farhad Fallahlalehzari - 27 Sep, 2018 - Comments: 0

Will the world be a better place in which to live by having autonomous cars driving around us? Or would it be unsafe and scary? Maybe someone was asking such a question even when the first steam-powered automobile capable of human transportation was built in 1769 [1]! As a person who likes driving, I wouldn’t like to have a ‘fully’ autonomous car, but I would like to get some assistanc... » read more

Domain Crossing Nightmares
By Brian Bailey - 27 Sep, 2018 - Comments: 1

Semiconductor Engineering sat down to discuss problems associated with domain crossings with Alex Gnusin, design verification technologist for Aldec; Pete Hardee, director, product management for Cadence; Joe Hupcey, product manager and verification product technologist for Mentor, a Siemens Business; Sven Beyer, product manager design verification for OneSpin; and Godwin Maben, applications en... » read more

56G 7nm SerDes: Eyewitness Account
By Mike Gianfagna - 27 Sep, 2018 - Comments: 0

High-performance SerDes represents critical enabling technology for advanced ASICs. This star IP block finds application in many networking and switching designs as well as other high-performance applications. So, when a new high-performance SerDes block hits the streets, it’s real news. eSilicon has been enjoying the spotlight on such an event. We recently announced silicon validation of our... » read more

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