Photonic-Electronic SmartNIC With Fast and Energy-Efficient Photonic Computing Cores (MIT)

A technical paper titled “Lightning: A Reconfigurable Photonic-Electronic SmartNIC for Fast and Energy-Efficient Inference” was published by researchers at Massachusetts Institute of Technology (MIT). Abstract: "The massive growth of machine learning-based applications and the end of Moore's law have created a pressing need to redesign computing platforms. We propose Lightning, the first ... » read more

3D-Integrated Neuromorphic Hardware With A Two-Level Neuromorphic “Synapse Over Neuron” Structure

A technical paper titled “3D Neuromorphic Hardware with Single Thin-Film Transistor Synapses Over Single Thin-Body Transistor Neurons by Monolithic Vertical Integration” was published by researchers at Korea Advanced Institute of Science and Technology (KAIST) and SK hynix. Abstract: "Neuromorphic hardware with a spiking neural network (SNN) can significantly enhance the energy efficiency... » read more

Design Optimization Of Split-Gate NOR Flash For Compute-In-Memory

A technical paper titled “Design Strategies of 40 nm Split-Gate NOR Flash Memory Device for Low-Power Compute-in-Memory Applications” was published by researchers at Seoul National University of Science and Technology and University of Seoul. Abstract: "The existing von Neumann architecture for artificial intelligence (AI) computations suffers from excessive power consumption and memo... » read more

Leveraging In-Package Wireless Technology To Improve The Thermal Behavior Of 2.5D Chiplet-Based SoP

A technical paper titled “REMOTE: Re-thinking Task Mapping on Wireless 2.5D Systems-on-Package for Hotspot Removal” was published by researchers at Swiss Federal Institute of Technology Lausanne (EPFL) and University of Applied Sciences and Arts of Western Switzerland (HES-SO). Abstract Excerpt "In this work, we propose a new task mapping heuristic that leverages in-package wireless t... » read more

Framework for Prototyping And In-Hardware Evaluation of Post-Quantum Cryptography HW Accelerators (TU Darmstadt)

A technical paper titled “PQC-HA: A Framework for Prototyping and In-Hardware Evaluation of Post-Quantum Cryptography Hardware Accelerators” was published by researchers at TU Darmstadt. Abstract: "In the third round of the NIST Post-Quantum Cryptography standardization project, the focus is on optimizing software and hardware implementations of candidate schemes. The winning schemes are ... » read more

Quantum Games Across Quantum Physics, Technologies, and Scientific Purposes 

A technical paper titled “The History of Quantum Games” was published by researchers at IBM Research and Aalto University. Abstract: "In this paper, we explore the historical development of playable quantum physics related games (quantum games). For the purpose of this examination, we have collected over 260 quantum games ranging from commercial games, applied and serious games, and games... » read more

Hardware Security for Silicon Photonic-Based AI Accelerators

A technical paper titled “Integrated Photonic AI Accelerators under Hardware Security Attacks: Impacts and Countermeasures” was published by researchers at Ecole Polytechnique de Montreal and Colorado State University. Abstract: "Integrated photonics based on silicon photonics platform is driving several application domains, from enabling ultra-fast chip-scale communication in high-perfor... » read more

Applying a Floating Gate Field Effect Transistor To A Logic-in-Memory Application Circuit Design

A technical paper titled “Analysis of Logic-in-Memory Full Adder Circuit With Floating Gate Field Effect Transistor (FGFET)” was published by researchers at Konkuk University, Korea National University of Transportation, Samsung Electronics, and Sungkyunkwan University. Abstract: "The high data throughput and high energy efficiency required recently are increasingly difficult to implement... » read more

Formally Verifying Data-Oblivious Behavior In HW Using Standard Property Checking Techniques

A technical paper titled “A Scalable Formal Verification Methodology for Data-Oblivious Hardware” was published by researchers at RPTU Kaiserslautern-Landau and Stanford University. Abstract: "The importance of preventing microarchitectural timing side channels in security-critical applications has surged in recent years. Constant-time programming has emerged as a best-practice technique... » read more

Hardware Platform For Evolving Robots

A technical paper titled “Practical hardware for evolvable robots” was published by researchers at University of York, Edinburgh Napier University, Vrije Universiteit Amsterdam, University of the West of England, and University of Sunderland. Abstract: "The evolutionary robotics field offers the possibility of autonomously generating robots that are adapted to desired tasks by iteratively... » read more

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