A Search Framework That Optimizes Hybrid-Device IMC Architectures For DNNs, Using Chiplets


A technical paper titled “HyDe: A Hybrid PCM/FeFET/SRAM Device-search for Optimizing Area and Energy-efficiencies in Analog IMC Platforms” was published by researchers at Yale University. Abstract: "Today, there are a plethora of In-Memory Computing (IMC) devices- SRAMs, PCMs & FeFETs, that emulate convolutions on crossbar-arrays with high throughput. Each IMC device offers its own pr... » read more

Analog Circuits Enabling Learning in Mixed-Signal Neuromorphic SNNs, With Tristate Stability and Weight Discretization Circuits


A technical paper titled “Neuromorphic analog circuits for robust on-chip always-on learning in spiking neural networks” was published by researchers at University of Zurich and ETH Zurich. Abstract: "Mixed-signal neuromorphic systems represent a promising solution for solving extreme-edge computing tasks without relying on external computing resources. Their spiking neural network circui... » read more

CNN Hardware Architecture With Weights Generator Module That Alleviates Impact Of The Memory Wall


A technical paper titled “Mitigating Memory Wall Effects in CNN Engines with On-the-Fly Weights Generation” was published by researchers at Samsung AI Center and University of Cambridge. Abstract: "The unprecedented accuracy of convolutional neural networks (CNNs) across a broad range of AI tasks has led to their widespread deployment in mobile and embedded settings. In a pursuit for high... » read more

A Photonic Circuit Architecture Allowing Faster, More Efficient Transfer of Large Amounts of Data


A technical paper titled "Massively scalable Kerr comb-driven silicon photonic link" was published by researchers at Columbia University and Air Force Research Laboratory. Abstract: "The growth of computing needs for artificial intelligence and machine learning is critically challenging data communications in today’s data-centre systems. Data movement, dominated by energy costs and limi... » read more

Improving Performance Of Artificial Intelligence And Quantum Computers


A technical paper titled “Gate-tunable superconducting diode effect in a three-terminal Josephson device” was published by researchers at University of Minnesota, University of California Santa Barbara, and Stanford University. Abstract: "The phenomenon of non-reciprocal critical current in a Josephson device, termed the Josephson diode effect, has garnered much recent interest. Realizati... » read more

SB MOSFET-Based Ultra-Low Power Real-Time Neurons for Neuromorphic Computing (Indian Institute of Technology)


A technical paper titled “Schottky Barrier MOSFET Enabled Ultra-Low Power Real-Time Neuron for Neuromorphic Computing” was published by researchers at the Indian Institute of Technology (IIT) Bombay. Abstract: "Energy-efficient real-time synapses and neurons are essential to enable large-scale neuromorphic computing. In this paper, we propose and demonstrate the Schottky-Barrier MOSFE... » read more

Chiplets: Bridging The Gap Between The System Requirements And Design Aggregation, Planning, And Optimization


A technical paper titled “System and Design Technology Co-optimization of Chiplet-based AI Accelerator with Machine Learning” was published by researchers at Auburn University. Abstract: "With the availability of advanced packaging technology and its attractive features, the chiplet-based architecture has gained traction among chip designers. The large design space and the lack of sys... » read more

Object Detection CNN Suitable For Edge Processors With Limited Memory


A technical paper titled “TinyissimoYOLO: A Quantized, Low-Memory Footprint, TinyML Object Detection Network for Low Power Microcontrollers” was published by researchers at ETH Zurich. Abstract: "This paper introduces a highly flexible, quantized, memory-efficient, and ultra-lightweight object detection network, called TinyissimoYOLO. It aims to enable object detection on microcontrol... » read more

A PIM Architecture That Supports Floating Point-Precision Computations Within The Memory Chip


A technical paper titled “FlutPIM: A Look-up Table-based Processing in Memory Architecture with Floating-point Computation Support for Deep Learning Applications” was published by researchers at Rochester Institute of Technology and George Mason University. Abstract: "Processing-in-Memory (PIM) has shown great potential for a wide range of data-driven applications, especially Deep Learnin... » read more

Comparing Analog and Digital SRAM In-Memory Computing Architectures (KU Leuven)


A technical paper titled "Benchmarking and modeling of analog and digital SRAM in-memory computing architectures" was published by researchers at KU Leuven. Abstract: "In-memory-computing is emerging as an efficient hardware paradigm for deep neural network accelerators at the edge, enabling to break the memory wall and exploit massive computational parallelism. Two design models have surge... » read more

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