category: Architectures

category: IoT, Security & Automotive

A Chiplet-Based Fully Homomorphic Encryption Accelerator
By Technical Paper Link - 18 Aug, 2023 - Comments: 0

A technical paper titled “CiFHER: A Chiplet-Based FHE Accelerator with a Resizable Structure” was published by researchers at Seoul National University. Abstract: "Fully homomorphic encryption (FHE) is in the spotlight as a definitive solution for privacy, but the high computational overhead of FHE poses a challenge to its practical adoption. Although prior studies have attempted to desig... » read more

Neuromorphic Computing: Graphene-Based Memristors For Future AI Hardware From Fabrication To SNNs
By Technical Paper Link - 15 Aug, 2023 - Comments: 0

A technical paper titled “A Review of Graphene-Based Memristive Neuromorphic Devices and Circuits” was published by researchers at James Cook University (Australia) and York University (Canada). Abstract: "As data processing volume increases, the limitations of traditional computers and the need for more efficient computing methods become evident. Neuromorphic computing mimics the brain's... » read more

New Architecture Elements For 5G RF Front-End Modules To Reduce Noise, Improve Efficiency, And Allow Multiple Radio Transmitters
By Technical Paper Link - 15 Aug, 2023 - Comments: 0

A technical paper titled “Circuits for 5G RF front-end modules” was published by researchers at Skyworks Solutions Inc. Abstract: "Worldwide adoption of fourth-generation wireless (4G) long-term evolution (LTE) smartphones and the actual transition to fifth-generation wireless (5G) is the main driving engine for semiconductor industry. 5G is expected to reach high data rate speeds (1 Gbps... » read more

A Performance-Aware Framework For Co-Optimizing Floorplan And Performance Of Chiplet-Based Architecture
By Technical Paper Link - 10 Aug, 2023 - Comments: 0

A technical paper titled “Floorplet: Performance-aware Floorplan Framework for Chiplet Integration” was published by researchers at Chinese University of Hong Kong and University of California Berkeley. Abstract: "A chiplet is an integrated circuit that encompasses a well-defined subset of an overall system's functionality. In contrast to traditional monolithic system-on-chips (SoCs),... » read more

A RISC-V Capability Architecture Orchestrating Compiler, Architecture, And System Designs For Full Memory Safety (Georgia Tech, Arm Research)
By Technical Paper Link - 08 Aug, 2023 - Comments: 0

A technical paper titled “RV-CURE: A RISC-V Capability Architecture for Full Memory Safety” was published by researchers at Georgia Institute of Technology and Arm Research. Abstract: "Despite decades of efforts to resolve, memory safety violations are still persistent and problematic in modern systems. Various defense mechanisms have been proposed, but their deployment in real systems re... » read more

Embedded GPU for FPGA, Achieving Over 770 MHz Operating Frequency With Unconstrained Compile
By Technical Paper Link - 02 Aug, 2023 - Comments: 0

A technical paper titled “eGPU: A 750 MHz Class Soft GPGPU for FPGA” was published by researchers at Intel Corporation and Imperial College London. Abstract: "This paper introduces the eGPU, a SIMT soft processor designed for FPGAs. Soft processors typically achieve modest operating frequencies, a fraction of the headline performance claimed by modern FPGA families, and obtain correspondi... » read more

Analog Circuits Enabling Learning in Mixed-Signal Neuromorphic SNNs, With Tristate Stability and Weight Discretization Circuits
By Technical Paper Link - 02 Aug, 2023 - Comments: 0

A technical paper titled “Neuromorphic analog circuits for robust on-chip always-on learning in spiking neural networks” was published by researchers at University of Zurich and ETH Zurich. Abstract: "Mixed-signal neuromorphic systems represent a promising solution for solving extreme-edge computing tasks without relying on external computing resources. Their spiking neural network circui... » read more

A Safety Island For Safe Use of HPC Devices For Safety-Critical Systems with RISC-V
By Technical Paper Link - 02 Aug, 2023 - Comments: 0

A technical paper titled “Envisioning a Safety Island to Enable HPC Devices in Safety-Critical Domains” was published by researchers at Barcelona Supercomputing Center and Intel. Abstract: "HPC (High Performance Computing) devices increasingly become the only alternative to deliver the performance needed in safety-critical autonomous systems (e.g., autonomous cars, unmanned planes) du... » read more

Programmable HW Accelerators For BGV Fully Homomorphic Encryption In The Cloud
By Technical Paper Link - 02 Aug, 2023 - Comments: 0

A technical paper titled “BASALISC: Programmable Hardware Accelerator for BGV Fully Homomorphic Encryption” was published by researchers at COSIC KU Leuven, Galois Inc., and Niobium Microsystems. Abstract: "Fully Homomorphic Encryption (FHE) allows for secure computation on encrypted data. Unfortunately, huge memory size, computational cost and bandwidth requirements limit its practic... » read more

CNN Hardware Architecture With Weights Generator Module That Alleviates Impact Of The Memory Wall
By Technical Paper Link - 01 Aug, 2023 - Comments: 0

A technical paper titled “Mitigating Memory Wall Effects in CNN Engines with On-the-Fly Weights Generation” was published by researchers at Samsung AI Center and University of Cambridge. Abstract: "The unprecedented accuracy of convolutional neural networks (CNNs) across a broad range of AI tasks has led to their widespread deployment in mobile and embedded settings. In a pursuit for high... » read more

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