category: Architectures

category: IoT, Security & Automotive

Chiplets For Generative AI Workloads: Challenges in both HW and SW
By Technical Paper Link - 29 Nov, 2023 - Comments: 0

A new technical paper titled "Challenges and Opportunities to Enable Large-Scale Computing via Heterogeneous Chiplets" was published by researchers at University of Pittsburgh, Lightelligence, and Meta. Abstract "Fast-evolving artificial intelligence (AI) algorithms such as large language models have been driving the ever-increasing computing demands in today's data centers. Heterogeneous c... » read more

Engineering chirality at wafer scale with ordered CNT architecture (Rice University and others)
By Technical Paper Link - 29 Nov, 2023 - Comments: 0

A new technical paper titled "Engineering chirality at wafer scale with ordered carbon nanotube architectures" was published by researchers at Rice University, University of Utah, J.A. Woollam Co. and Tokyo Metropolitan University. Abstract "Creating artificial matter with controllable chirality in a simple and scalable manner brings new opportunities to diverse areas. Here we show two su... » read more

A Fast And Unified Toolchain For Rapid Design Space Exploration Of Chiplet Architectures
By Technical Paper Link - 27 Nov, 2023 - Comments: 0

A technical paper titled “RapidChiplet: A Toolchain for Rapid Design Space Exploration of Chiplet Architectures” was published by researchers at ETH Zurich and University of Bologna. Abstract: "Chiplet architectures are a promising paradigm to overcome the scaling challenges of monolithic chips. Chiplets offer heterogeneity, modularity, and cost-effectiveness. The design space of chiplet ... » read more

Fast Interrupt Extension For MCU RISC-V
By Technical Paper Link - 20 Nov, 2023 - Comments: 0

A technical paper titled “CV32RT: Enabling Fast Interrupt and Context Switching for RISC-V Microcontrollers” was published by researchers at ETH Zurich and University of Bologna. Abstract: "Processors using the open RISC-V ISA are finding increasing adoption in the embedded world. Many embedded use cases have real-time constraints and require flexible, predictable, and fast reactive handl... » read more

Continuous Energy Monte Carlo Particle Transport On AI HW Accelerators
By Technical Paper Link - 20 Nov, 2023 - Comments: 0

A technical paper titled “Efficient Algorithms for Monte Carlo Particle Transport on AI Accelerator Hardware” was published by researchers at Argonne National Laboratory, University of Chicago, and Cerebras Systems. Abstract: "The recent trend toward deep learning has led to the development of a variety of highly innovative AI accelerator architectures. One such architecture, the Cerebras... » read more

Neuromorphic Devices Based On Memristive Nanowire Networks
By Technical Paper Link - 16 Nov, 2023 - Comments: 0

A technical paper titled “Online dynamical learning and sequence memory with neuromorphic nanowire networks” was published by researchers at University of Sydney, University of California Los Angeles (UCLA), National Institute for Materials Science (NIMS), Kyushu Institute of Technology (Kyutech), and University of Sydney Nano Institute. Abstract: "Nanowire Networks (NWNs) belong to an em... » read more

Analog In-Memory Cores With Multi-Memristive Unit-Cells (IBM)
By Technical Paper Link - 14 Nov, 2023 - Comments: 0

A technical paper titled “Exploiting the State Dependency of Conductance Variations in Memristive Devices for Accurate In-Memory Computing” was published by researchers at IBM Research-Europe, IBM Research-Albany, and IBM Research-Yorktown Heights. Abstract: "Analog in-memory computing (AIMC) using memristive devices is considered a promising Non-von Neumann approach for deep learning (DL... » read more

A HIL Methodology For The SoC Development Flow
By Technical Paper Link - 14 Nov, 2023 - Comments: 0

A technical paper titled “Virtual-Peripheral-in-the-Loop : A Hardware-in-the-Loop Strategy to Bridge the VP/RTL Design-Gap” was published by researchers at University of Bremen and German Research Center for Artificial Intelligence (DFKI). Abstract: "Virtual Prototypes act as an executable specification model, offering a unified behavior reference model for SW and HW engineers. However, b... » read more

CMOS-Based HW Topology For Single-Cycle In-Memory XOR/XNOR Operations
By Technical Paper Link - 07 Nov, 2023 - Comments: 0

A technical paper titled “CMOS-based Single-Cycle In-Memory XOR/XNOR” was published by researchers at University of Tennessee, University of Virginia, and Oak Ridge National Laboratory (ORNL). Abstract: "Big data applications are on the rise, and so is the number of data centers. The ever-increasing massive data pool needs to be periodically backed up in a secure environment. Moreover, a ... » read more

A Survey Of Recent Advances And Research Activities In Wireless NoC Security
By Technical Paper Link - 07 Nov, 2023 - Comments: 0

A technical paper titled “Wireless Network-on-Chip Security Review: Attack Taxonomy, Implications, and Countermeasures” was published by researchers at Macquarie University (Sydney). Abstract: "Network-on-chip (NoC) is a critical on-chip communication framework that underpins high-performance multicore computing and network system architectures. Its adoption has become widespread due to t... » read more

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