category: Architectures

category: IoT, Security & Automotive

FPGA-based Infrastructure, With RISC-V Prototype, to Enable Implementation & Evaluation of Cross-Layer Techniques in Real HW (Best Paper Award)
By Technical Paper Link - 15 Mar, 2023 - Comments: 0

A technical paper titled "MetaSys: A Practical Open-Source Metadata Management System to Implement and Evaluate Cross-Layer Optimizations" was published by researchers at University of Toronto, ETH Zurich, and Carnegie Mellon University. This paper won the Best Paper Award at the HiPEAC 2023 conference. Abstract: "This paper introduces the first open-source FPGA-based infrastructure, MetaSy... » read more

Learning The AMS Circuit Representation From Layout Positions (UT Austin/ NVIDIA)
By Technical Paper Link - 15 Mar, 2023 - Comments: 0

A recent technical paper titled "TAG: Learning Circuit Spatial Embedding From Layouts" was published by researchers at UT Austin and NVIDIA. Abstract "Analog and mixed-signal (AMS) circuit designs still rely on human design expertise. Machine learning has been assisting circuit design automation by replacing human experience with artificial intelligence. This paper presents TAG, a new parad... » read more

Co-Design View of Cross-Bar Based Compute-In-Memory
By Technical Paper Link - 15 Mar, 2023 - Comments: 0

A new review paper titled "Compute in-Memory with Non-Volatile Elements for Neural Networks: A Review from a Co-Design Perspective" was published by researchers at Argonne National Lab, Purdue University, and Indian Institute of Technology Madras. "With an over-arching co-design viewpoint, this review assesses the use of cross-bar based CIM for neural networks, connecting the material proper... » read more

FPGAs: Automated Framework For Architecture-Space Exploration of Approximate Accelerators
By Technical Paper Link - 10 Mar, 2023 - Comments: 0

A technical paper titled "autoXFPGAs: An End-to-End Automated Exploration Framework for Approximate Accelerators in FPGA-Based Systems" was published (preprint) by researchers at TU Wien, Brno University of Technology, and NYUAD. Abstract "Generation and exploration of approximate circuits and accelerators has been a prominent research domain exploring energy-efficiency and/or performance... » read more

Hardware-Based Confidential Computing (NIST)
By Technical Paper Link - 10 Mar, 2023 - Comments: 0

NIST has published a draft report, titled “Hardware Enabled Security: Hardware-Based Confidential Computing,” which presents an approach for managing machine identities for protection against malware and other security vulnerabilities. Comments are due April 10, 2023. Abstract "Organizations employ a growing volume of machine identities, often numbering in the thousands or millions per ... » read more

SpGEMM Targeting RISC-V Vector Processors (Barcelona Supercomputing Center)
By Technical Paper Link - 10 Mar, 2023 - Comments: 0

A new technical paper titled "Optimization of SpGEMM with Risc-V vector instructions" was published (preprint) by researchers at the Barcelona Supercomputing Center. Abstract "The Sparse GEneral Matrix-Matrix multiplication (SpGEMM) C=A×B is a fundamental routine extensively used in domains like machine learning or graph analytics. Despite its relevance, the efficient execution of SpGEMM ... » read more

Hardware Virtualization Support in the RISC-V CVA6 Core
By Technical Paper Link - 08 Mar, 2023 - Comments: 0

A new technical paper titled "CVA6 RISC-V Virtualization: Architecture, Microarchitecture, and Design Space Exploration" was published (preprint) by researchers at Universidade do Minho, University of Bologna, and ETH Zurich. Abstract "Virtualization is a key technology used in a wide range of applications, from cloud computing to embedded systems. Over the last few years, mainstream comp... » read more

CXL-Based Memory Pooling System Meets Cloud Performance Goals And Significantly Reduces DRAM Cost
By Technical Paper Link - 05 Mar, 2023 - Comments: 0

A technical paper titled "Pond: CXL-Based Memory Pooling Systems for Cloud Platforms" was published by researchers at Virginia Tech, Intel, Microsoft Azure, Google, and Stone Co. Abstract "Public cloud providers seek to meet stringent performance requirements and low hardware cost. A key driver of performance and cost is main memory. Memory pooling promises to improve DRAM utilization and t... » read more

Using Formal Verification To Optimize HLS-Produced Circuits (ETH Zurich)
By Technical Paper Link - 05 Mar, 2023 - Comments: 0

A new technical paper titled "Eliminating Excessive Dynamism of Dataflow Circuits Using Model Checking" was published by researchers at ETH Zurich. Abstract "Recent HLS efforts explore the generation of dynamically scheduled, dataflow circuits from high-level code; their ability to adapt the schedule at runtime to particular data and control outcomes promises superior performance to standar... » read more

Fast Parallel Multi-HDL Compiler (UC Santa Cruz)
By Technical Paper Link - 04 Mar, 2023 - Comments: 0

A technical paper titled "A Multi-threaded Fast Hardware Compiler for HDL" was published by researchers at UC Santa Cruz. Abstract: "A set of new Hardware Description Languages (HDLs) are emerging to ease hardware design. HDL compilation time is a major bottleneck in the designer’s productivity. Moreover, as the HDLs are developed independently, the possibility to share innovations in com... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy