category: Architectures

category: IoT, Security & Automotive

Costs of Static HW Partitioning on RISC-V
By Technical Paper Link - 25 Aug, 2022 - Comments: 0

A new technical paper titled "Static Hardware Partitioning on RISC-V -- Shortcomings, Limitations, and Prospects" was published by researchers at Technical University of Applied Sciences (Regensburg, Germany) and Siemens AG (Corporate Research). Abstract "On embedded processors that are increasingly equipped with multiple CPU cores, static hardware partitioning is an established means of c... » read more

Novel In-Pixel-in-Memory (P2M) Paradigm for Edge Intelligence (USC)
By Technical Paper Link - 24 Aug, 2022 - Comments: 0

A new technical paper titled "A processing-in-pixel-in-memory paradigm for resource-constrained TinyML applications" was published by researchers at University of Southern California (USC). According to the paper, "we propose a novel Processing-in-Pixel-in-memory (P2M) paradigm, that customizes the pixel array by adding support for analog multi-channel, multi-bit convolution, batch normaliza... » read more

Polynesia, A Novel Hardware/Software Cooperative Design for In-Memory HTAP Databases
By Technical Paper Link - 22 Aug, 2022 - Comments: 0

A team of researchers from ETH Zurich, Google and Univ. of Illinois Urbana-Champaign recently published a technical paper titled "Polynesia: Enabling High-Performance and Energy-Efficient Hybrid Transactional/Analytical Databases with Hardware/Software Co-Design". Abstract (partial) "We propose Polynesia, a hardware–software co-designed system for in-memory HTAP [hybrid transactional/anal... » read more

Gemmini: Open-source, Full-Stack DNN Accelerator Generator (DAC Best Paper)
By Technical Paper Link - 19 Aug, 2022 - Comments: 0

This technical paper titled "Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integration" was published jointly by researchers at UC Berkeley and a co-author from MIT.  The research was partially funded by DARPA and won DAC 2021 Best Paper. The paper presents Gemmini, "an open-source, full-stack DNN accelerator generator for DNN workloads, enabling end-to-e... » read more

Advances In Reconfigurable Intelligent Surfaces Hardware Architectures: Beyond 5G/6G
By Technical Paper Link - 19 Aug, 2022 - Comments: 0

This technical paper titled "Reconfigurable Intelligent Surfaces for Wireless Communications: Overview of Hardware Designs, Channel Models, and Estimation Techniques" is from researchers at IEEE. The paper's abstract states "we overview and taxonomize the latest advances in RIS [reconfigurable intelligent surfaces] hardware architectures as well as the most recent developments in the modelin... » read more

Implementing Cryptographic Algorithms for the RISC-V Instruction Set Architecture in Two Cases
By Technical Paper Link - 18 Aug, 2022 - Comments: 0

This new technical paper titled "Symmetric Cryptography on RISC-V: Performance Evaluation of Standardized Algorithms" was published by researchers at Intel, North Arizona University and Google, with partial funding from U.S. Air Force Research Laboratory. Abstract "The ever-increasing need for securing computing systems using cryptographic algorithms is spurring interest in the efficient i... » read more

ISO-26262 Hardware Architecture
By Technical Paper Link - 18 Aug, 2022 - Comments: 0

This new technical paper titled "Safety-Oriented System Hardware Architecture Exploration in Compliance with ISO 26262" was published by researchers at National Taipei University. Abstract "Safety-critical intelligent automotive systems require stringent dependability while the systems are in operation. Therefore, safety and reliability issues must be addressed in the development of such sa... » read more

Efficient Neuromorphic AI Chip: “NeuroRRAM”
By Technical Paper Link - 17 Aug, 2022 - Comments: 0

New technical paper titled "A compute-in-memory chip based on resistive random-access memory" was published by a team of international researchers at Stanford, UCSD, University of Pittsburgh, University of Notre Dame and Tsinghua University. The paper's abstract states "by co-optimizing across all hierarchies of the design from algorithms and architecture to circuits and devices, we present ... » read more

Heterogenous Computing & Cache Attacks
By Technical Paper Link - 12 Aug, 2022 - Comments: 0

Researchers at imec-COSIC, KU Leuven presented this paper titled "Double Trouble: Combined Heterogeneous Attacks on Non-Inclusive Cache Hierarchies" at the USENIX Security Symposium in Boston in August 2022. Note, this is a prepublication paper. Abstract: "As the performance of general-purpose processors faces diminishing improvements, computing systems are increasingly equipped with domai... » read more

Microarchitectural Side-Channel Attacks and Mitigations on the On-Chip Mesh Interconnect
By Technical Paper Link - 11 Aug, 2022 - Comments: 0

This new technical paper titled "Don't Mesh Around: Side-Channel Attacks and Mitigations on Mesh Interconnects" was presented by researchers at University of Illinois at Urbana-Champaign, MIT, and Texas Advanced Computing Center at the USENIX Security Symposium in Boston in August 2022. Abstract: "This paper studies microarchitectural side-channel attacks and mitigations on the on-chip mes... » read more

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