category: Architectures

category: IoT, Security & Automotive

Optimizing Hardware Capacity, Utilizing Automatic Differentiation to Efficiently Compute Derivatives in Parallel Programming Models
By Technical Paper Link - 30 Nov, 2022 - Comments: 0

A technical paper titled "Scalable Automatic Differentiation of Multiple Parallel Paradigms through Compiler Augmentation" was published by researchers at MIT (CSAIL), Argonne National Lab, and TU Munich. The paper was a Best Paper Finalist and a Best Student Paper winner at SuperComputing 2022. Find the technical paper here. Published November 2022. The work "demonstrates how Enzyme opti... » read more

Profile-Guided HW/SW Mechanism To Efficiently Reduce Branch Mispredictions In Data Center Applications (Best Paper Award)
By Technical Paper Link - 17 Nov, 2022 - Comments: 0

A new technical paper titled "Whisper: Profile-Guided Branch Misprediction Elimination for Data Center Applications" was published by researchers at University of Michigan, ARM, University of California, Santa Cruz, and Texas A&M University. This work was awarded a best paper award at October's 2022 Institute of Electrical and Electronics Engineers (IEEE)/Association for Computing Machin... » read more

Approximate Adders Suitable For In-Memory Computing Using a Memristor Crossbar Array
By Technical Paper Link - 17 Nov, 2022 - Comments: 0

A new technical paper titled "IMAGIN: Library of IMPLY and MAGIC NOR Based Approximate Adders for In-Memory Computing" was published by researchers at DFKI (German Research Center for Artificial Intelligence) and Indian Institute of Information Technology Guwahati. "We developed a framework to generate approximate adder designs with varying output errors for 8, 12, and 16-bit adders. We imp... » read more

Memory and Energy-Efficient Batch Normalization Hardware
By Technical Paper Link - 17 Nov, 2022 - Comments: 0

A new technical paper titled "LightNorm: Area and Energy-Efficient Batch Normalization Hardware for On-Device DNN Training" was published by researchers at DGIST (Daegu Gyeongbuk Institute of Science and Technology). The work was supported by Samsung Research Funding Incubation Center. Abstract: "When training early-stage deep neural networks (DNNs), generating intermediate features via con... » read more

Multi-Bit In-Memory Computing System for HDC using FeFETs, Achieving SW-Equivalent-Accuracies
By Technical Paper Link - 11 Nov, 2022 - Comments: 0

A new technical paper titled "Achieving software-equivalent accuracy for hyperdimensional computing with ferroelectric-based in-memory computing" by researchers at University of Notre Dame, Fraunhofer Institute for Photonic Microsystems, University of California Irvine, and Technische Universität Dresden. "We present a multi-bit IMC system for HDC using ferroelectric field-effect transistor... » read more

Energy of Computing As A Key Design Aspect (SLAC/Stanford, MIT)
By Technical Paper Link - 08 Nov, 2022 - Comments: 0

A technical paper titled "Trends in Energy Estimates for Computing in AI/Machine Learning Accelerators, Supercomputers, and Compute-Intensive Applications" was published by researchers at SLAC/Stanford University and MIT. Abstract: "We examine the computational energy requirements of different systems driven by the geometrical scaling law, and increasing use of Artificial Intelligence or Ma... » read more

Scalable Optical AI Accelerator Based on a Crossbar Architecture
By Technical Paper Link - 08 Nov, 2022 - Comments: 0

A new technical paper titled "Scalable Coherent Optical Crossbar Architecture using PCM for AI Acceleration" was published by researchers at University of Washington. Abstract: "Optical computing has been recently proposed as a new compute paradigm to meet the demands of future AI/ML workloads in datacenters and supercomputers. However, proposed implementations so far suffer from lack of sc... » read more

L-FinFET Neuron For A Highly Scalable Capacitive Neural Network (KAIST)
By Technical Paper Link - 31 Oct, 2022 - Comments: 0

A new technical paper titled "An Artificial Neuron with a Leaky Fin-Shaped Field-Effect Transistor for a Highly Scalable Capacitive Neural Network" was published by researchers at KAIST (Korea Advanced Institute of Science and Technology). “In commercialized flash memory, tunnelling oxide prevents the trapped charges from escaping for better memory ability. In our proposed FinFET neuron, t... » read more

Side-Channel Secure Translation Lookaside Buffer Architecture
By Technical Paper Link - 28 Oct, 2022 - Comments: 0

A new technical paper titled "Risky Translations: Securing TLBs against Timing Side Channels" was posted by researchers at Ruhr University Bochum (Germany) and Cyber-Physical Systems of the German Research Center for Artificial Intelligence (DFKI). Abstract: "Microarchitectural side-channel vulnerabilities in modern processors are known to be a powerful attack vector that can be utilized to... » read more

In-NAND Flash Processing Technique for Improved Performance, Energy Efficiency & Reliability of Bulk Bitwise Operations
By Technical Paper Link - 26 Oct, 2022 - Comments: 0

A new technical paper titled "Flash-Cosmos: In-Flash Bulk Bitwise Operations Using Inherent Computation Capability of NAND Flash Memory" was published by researchers at ETH Zurich, POSTECH, LIRMM/Univ. Montpellier/CNRS and Kyungpook National University. Find the technical paper here (published September 2022) and related YouTube lecture here. "We propose Flash-Cosmos (Flash Computation wi... » read more

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