category: Architectures

category: IoT, Security & Automotive

Adaptive RISC-V Cache Architecture for Near-Memory Extensions (Politecnico di Torino, EPFL)
By Technical Paper Link - 04 Apr, 2025 - Comments: 0

A new technical paper titled "ARCANE: Adaptive RISC-V Cache Architecture for Near-memory Extensions" was published by researchers at Politecnico di Torino and EPFL. Abstract "Modern data-driven applications expose limitations of von Neumann architectures - extensive data movement, low throughput, and poor energy efficiency. Accelerators improve performance but lack flexibility and require... » read more

Reverse Engineering NVIDIA GPU Cores (Universitat Politècnica de Catalunya)
By Technical Paper Link - 30 Mar, 2025 - Comments: 0

A new technical paper titled "Analyzing Modern NVIDIA GPU cores" was published by Universitat Politècnica de Catalunya. Abstract "GPUs are the most popular platform for accelerating HPC workloads, such as artificial intelligence and science simulations. However, most microarchitectural research in academia relies on GPU core pipeline designs based on architectures that are more than 15 yea... » read more

Scalable And Energy Efficient Solution for Hardware-Based ANNs (KAUST, NUS)
By Technical Paper Link - 30 Mar, 2025 - Comments: 0

A new technical paper titled "Synaptic and neural behaviours in a standard silicon transistor" was published by researchers at KAUST and National University of Singapore. Abstract "Hardware implementations of artificial neural networks (ANNs)—the most advanced of which are made of millions of electronic neurons interconnected by hundreds of millions of electronic synapses—have achieved ... » read more

GPU Analysis Identifying Performance Bottlenecks That Cause Throughput Plateaus In Large-Batch Inference
By Technical Paper Link - 30 Mar, 2025 - Comments: 1

A new technical paper titled "Mind the Memory Gap: Unveiling GPU Bottlenecks in Large-Batch LLM Inference" was published by researchers at Barcelona Supercomputing Center, Universitat Politecnica de Catalunya, and IBM Research. Abstract "Large language models have been widely adopted across different tasks, but their auto-regressive generation nature often leads to inefficient resource util... » read more

Fully Digital Adaptive PMU-MCU System For Hybrid (Battery-Harvester) IoT Devices
By Technical Paper Link - 25 Mar, 2025 - Comments: 0

A new technical paper titled "An Ultra-Low-Leakage Microcontroller with Configurable Power Management for Energy Harvesting IoT Devices" was published by researchers at Eindhoven University of Technology and Innatera Nanosystems. Abstract "This paper presents a power management unit (PMU) architecture designed for energy-harvesting IoT devices, integrating a dual-capacitor system, an ultra-... » read more

HW Implementation Of An ONN Coupled By A ReRAM Crossbar Array (IBM, TU Eindhoven)
By Technical Paper Link - 25 Mar, 2025 - Comments: 0

A new technical paper titled "Hardware Implementation of Ring Oscillator Networks Coupled by BEOL Integrated ReRAM for Associative Memory Tasks" was published by researchers at IBM Research Europe and Eindhoven University of Technology. Abstract "We demonstrate the first hardware implementation of an oscillatory neural network (ONN) utilizing resistive memory (ReRAM) for coupling elements. ... » read more

Evaluation Tool For The Cost Impacts Of Chiplet-Specific Design Choices
By Technical Paper Link - 25 Mar, 2025 - Comments: 0

A new technical paper titled "CATCH: a Cost Analysis Tool for Co-optimization of chiplet-based Heterogeneous systems" was published by researchers at UCLA, Duke University and Arizona State University. Abstract "With the increasing prevalence of chiplet systems in high-performance computing applications, the number of design options has increased dramatically. Instead of chips defaulting to... » read more

3D Photonic Integration For Ultra-Low-Energy, High-Bandwidth Interchip Data Links (Columbia et al.)
By Linda Christensen - 23 Mar, 2025 - Comments: 0

A new technical paper titled "Three-dimensional photonic integration for ultra-low-energy, high-bandwidth interchip data links" was published by researchers at Columbia University, Cornell University, Air Force Research Laboratory Information Directorate and Dartmouth College. Abstract "Artificial intelligence (AI) hardware is positioned to unlock revolutionary computational abilities by ... » read more

Design Optimization Techniques To Improve NC-CFET Performance
By Technical Paper Link - 14 Mar, 2025 - Comments: 0

A new technical paper titled "Insights Into Design Optimization of Negative Capacitance Complementary-FET (CFET)" was published by researchers at National Yang Ming Chiao Tung University. Abstract "This work assesses and analyzes negative-capacitance CFETs (NC-CFETs) with metal-ferroelectric-insulator-semiconductor (MFIS) and metal-ferroelectric-metal-insulator-semiconductor (MFMIS) configu... » read more

Energy-Efficient Scalable Silicon Photonic Platform For AI Accelerator HW
By Technical Paper Link - 12 Mar, 2025 - Comments: 0

A new technical paper titled "Large-Scale Integrated Photonic Device Platform for Energy-Efficient AI/ML Accelerators" was published by researchers at HP Labs, IIT Madras, Microsoft Research and University of Michigan. Abstract "The convergence of deep learning and Big Data has spurred significant interest in developing novel hardware that can run large artificial intelligence (AI) workload... » read more

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