category: Architectures

category: IoT, Security & Automotive

The Optical Implementation of Backpropagation (Oxford, Lumai)
By Technical Paper Link - 07 Mar, 2025 - Comments: 0

A technical paper titled "Training neural networks with end-to-end optical backpropagation" was published by researchers at University of Oxford and Lumai Ltd. Abstract "Optics is an exciting route for the next generation of computing hardware for machine learning, promising several orders of magnitude enhancement in both computational speed and energy efficiency. However, reaching the full... » read more

Field-Coupled Nanocomputing: Scalable And Efficient Post-Layout Optimization (TU Munich)
By Technical Paper Link - 07 Mar, 2025 - Comments: 0

A new technical paper titled "Efficient and Scalable Post-Layout Optimization for Field-coupled Nanotechnologies" was published by researcher at the Technical University of Munich (TUM). Abstract "As conventional computing technologies approach their physical limits, the quest for increased computational power intensifies, heightening interest in post-CMOS technologies. Among these, Field... » read more

Solution To Read Disturbance For Current And Future DRAM Chips at Low Area, Performance And Energy Costs (ETH Zurich et al.)
By Technical Paper Link - 07 Mar, 2025 - Comments: 0

A new technical paper titled "Chronus: Understanding and Securing the Cutting-Edge Industry Solutions to DRAM Read Disturbance" was published by researchers at ETH Zurich, TOBB, and University of Sharjah. Abstract "We 1) present the first rigorous security, performance, energy, and cost analyses of the state-of-the-art on-DRAM-die read disturbance mitigation method, Per Row Activation Count... » read more

Understanding Fault Injection Attacks At The Pre-Silicon Level
By Technical Paper Link - 07 Mar, 2025 - Comments: 0

A new technical paper titled "CRAFT: Characterizing and Root-Causing Fault Injection Threats at Pre-Silicon" was published by researchers at North Carolina State University. Abstract "Fault injection attacks represent a class of threats that can compromise embedded systems across multiple layers of abstraction, such as system software, instruction set architecture (ISA), microarchitecture, ... » read more

RISC-V High Performance Multicore and GPU SoC Platform For Safety Critical System
By Technical Paper Link - 03 Mar, 2025 - Comments: 0

A new technical paper titled "A RISC-V Multicore and GPU SoC Platform with a Qualifiable Software Stack for Safety Critical Systems" published by researchers at Universitat Politecnica de Catalunya and Barcelona Supercomputing Center. Abstract "In the context of the Horizon Europe project, METASAT, a hardware platform was developed as a prototype of future space systems. The platform is bas... » read more

3D Stacked Device Architecture Enabled By BEOL-Compatible Transistors (Stanford et al.)
By Technical Paper Link - 26 Feb, 2025 - Comments: 0

A new technical paper titled "Omni 3D: BEOL-Compatible 3-D Logic With Omnipresent Power, Signal, and Clock" was published by researchers at Stanford University, Intel Corporation and Carnegie Mellon University. Abstract "This article presents Omni 3D—a 3-D-stacked device architecture that is naturally enabled by back-end-of-line (BEOL)-compatible transistors. Omni 3D interleaves metal lay... » read more

SW-HW Co-Design Mitigation To Strengthen ASLR Against Microarchitectural Attacks (MIT)
By Technical Paper Link - 26 Feb, 2025 - Comments: 0

A technical paper titled "Oreo: Protecting ASLR Against Microarchitectural Attacks" was published by researchers at MIT. Abstract "Address Space Layout Randomization (ASLR) is one of the most prominently deployed mitigations against memory corruption attacks. ASLR randomly shuffles program virtual addresses to prevent attackers from knowing the location of program contents in memory. Microa... » read more

Design Space For The Device-Circuit Codesign Of NVM-Based CIM Accelerators (TSMC)
By Technical Paper Link - 24 Feb, 2025 - Comments: 0

A new technical paper titled "Assessing Design Space for the Device-Circuit Codesign of Nonvolatile Memory-Based Compute-in-Memory Accelerators" was published by TSMC researchers. Abstract "Unprecedented penetration of artificial intelligence (AI) algorithms has brought about rapid innovations in electronic hardware, including new memory devices. Nonvolatile memory (NVM) devices offer one s... » read more

Cradle-To-Grave Analysis Of The Carbon Footprint of AI Hardware (Google)
By Technical Paper Link - 24 Feb, 2025 - Comments: 0

A new technical paper titled "Life-Cycle Emissions of AI Hardware: A Cradle-To-Grave Approach and Generational Trends" was published by researchers at Google. Abstract "Specialized hardware accelerators aid the rapid advancement of artificial intelligence (AI), and their efficiency impacts AI's environmental sustainability. This study presents the first publication of a comprehensive AI acc... » read more

Low-Cost TSV Repair Architecture Specialized for Highly Clustered TSV Faults Within HBM
By Technical Paper Link - 20 Feb, 2025 - Comments: 0

A new technical paper titled "Low Cost TSV Repair Architecture Using Switch-Based Matrix for Highly Clustered Faults" was published by researchers at Yonsei University. Abstract "Through-silicon via (TSV), responsible for inter-layer communication in high-bandwidth memory (HBM), plays a critical role in HBM operation. Therefore, faults occur in TSVs can critically impact the entire chips. H... » read more

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