LLM-Aided AI Accelerator Design Automation (Georgia Tech)

A technical paper titled “GPT4AIGChip: Towards Next-Generation AI Accelerator Design Automation via Large Language Models” was published by researchers at Georgia Institute of Technology. Abstract: "The remarkable capabilities and intricate nature of Artificial Intelligence (AI) have dramatically escalated the imperative for specialized AI accelerators. Nonetheless, designing these accele... » read more

LLM-Assisted Generation Of Formal Verification Testbenches: RTL to SVA (Princeton)

A technical paper titled “From RTL to SVA: LLM-assisted generation of Formal Verification Testbenches” was published by researchers at Princeton University. Abstract: "Formal property verification (FPV) has existed for decades and has been shown to be effective at finding intricate RTL bugs. However, formal properties, such as those written as System Verilog Assertions (SVA), are time-con... » read more

Improving ML-Based Device Modeling Using Variational Autoencoder Techniques

A technical paper titled “Improving Semiconductor Device Modeling for Electronic Design Automation by Machine Learning Techniques” was published by researchers at Commonwealth Scientific and Industrial Research Organisation (CSIRO), Peking University, National University of Singapore, and University of New South Wales. Abstract: "The semiconductors industry benefits greatly from the integ... » read more

Formally Verifying Data-Oblivious Behavior In HW Using Standard Property Checking Techniques

A technical paper titled “A Scalable Formal Verification Methodology for Data-Oblivious Hardware” was published by researchers at RPTU Kaiserslautern-Landau and Stanford University. Abstract: "The importance of preventing microarchitectural timing side channels in security-critical applications has surged in recent years. Constant-time programming has emerged as a best-practice technique... » read more

Hardware Platform For Evolving Robots

A technical paper titled “Practical hardware for evolvable robots” was published by researchers at University of York, Edinburgh Napier University, Vrije Universiteit Amsterdam, University of the West of England, and University of Sunderland. Abstract: "The evolutionary robotics field offers the possibility of autonomously generating robots that are adapted to desired tasks by iteratively... » read more

Formal Verification Of a Sequestered Encryption Architecture

A technical paper titled “Security Verification of Low-Trust Architectures” was published by researchers at Princeton University, University of Michigan, and Lafayette College. Abstract: "Low-trust architectures work on, from the viewpoint of software, always-encrypted data, and significantly reduce the amount of hardware trust to a small software-free enclave component. In this paper, we... » read more

DRAM Simulator For Evaluation of Memory System Design Changes (ETH Zurich)

A technical paper titled “Ramulator 2.0: A Modern, Modular, and Extensible DRAM Simulator” was published by researchers at ETH Zurich. Abstract: "We present Ramulator 2.0, a highly modular and extensible DRAM simulator that enables rapid and agile implementation and evaluation of design changes in the memory controller and DRAM to meet the increasing research effort in improving the perfo... » read more

A Microfluidics Device That Can Perform ANN Computation On Data Stored In DNA

A technical paper titled “Neural network execution using nicked DNA and microfluidics” was published by researchers at University of Minnesota Twin-Cities and Rochester Institute of Technology. Abstract: "DNA has been discussed as a potential medium for data storage. Potentially it could be denser, could consume less energy, and could be more durable than conventional storage media such a... » read more

An Open-Source Solution To Accelerate Autonomous Vehicle Validation And Verification Research

A technical paper titled “PolyVerif: An Open-Source Environment for Autonomous Vehicle Validation and Verification Research Acceleration” was published by researchers at Florida Polytechnic University, Embry-Riddle Aeronautical University, Tallinn University of Technology, and Acclivis Technologies. Abstract: "Validation and Verification (V&V) of Artificial Intelligence (AI) based cyb... » read more

An Open-Source Hardware Design And Specification Language To Improve Productivity And Verification 

A technical paper titled “PEak: A Single Source of Truth for Hardware Design and Verification” was published by researchers at Stanford University. Abstract: "Domain-specific languages for hardware can significantly enhance designer productivity, but sometimes at the cost of ease of verification. On the other hand, ISA specification languages are too static to be used during early stage d... » read more

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