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Coverage-Directed Test Selection Method for Automatic Test Biasing During Simulation-Based Verification


New research paper titled "Supervised Learning for Coverage-Directed Test Selection in Simulation-Based Verification" from researchers at University of Bristol and Infineon Technologies. Abstract: "Constrained random test generation is one the most widely adopted methods for generating stimuli for simulation-based verification. Randomness leads to test diversity, but tests tend to repeate... » read more

Designing and Simulating Low-Voltage CMOS Circuits Using Four-Parameter Model


New technical paper titled "Bridging the Gap between Design and Simulation of Low-Voltage CMOS Circuits" from researchers at Federal University of Santa Catarina, Brazil. Abstract "This work proposes a truly compact MOSFET model that contains only four parameters to assist an integrated circuits (IC) designer in a design by hand. The four-parameter model (4PM) is based on the advanced com... » read more

Hardware Dynamic IFT Mechanism That Scales to Complex Open-Source RISC-V Processors


New technical paper titled "CellIFT: Leveraging Cells for Scalable and Precise Dynamic Information Flow Tracking in Hardware Designs" by researchers at ETH Zurich and Intel.  Paper to be presented at USENIX Security 2022 (August 10-12, 2022) in Boston, MA, USA. Partial Abstract "We introduce CELLIFT, a new design point in the space of dynamic IFT [Information flow tracking] for hardware. C... » read more

U. Of Florida: Protecting Chip-Design IP From Reverse-Engineering


New research paper titled "Hardening Circuit-Design IP Against Reverse-Engineering Attacks" from University of Florida. "Design-hiding techniques are a central piece of academic and industrial efforts to protect electronic circuits from being reverse-engineered. However, these techniques have lacked a principled foundation to guide their design and security evaluation, leading to a long line... » read more

MIT: Stackable AI Chip With Lego-style Design


New technical paper titled "Reconfigurable heterogeneous integration using stackable chips with embedded artificial intelligence" from researchers at MIT, along with Harvard University, Tsinghua University, Zhejiang University, and others. Partial Abstract: "Here we report stackable hetero-integrated chips that use optoelectronic device arrays for chip-to-chip communication and neuromorphic... » read more

CORDIC-based Chip Design With Iterative Pipelining Architecture for Biped Robots


New technical paper titled "Efficient and Accurate CORDIC Pipelined Architecture Chip Design Based on Binomial Approximation for Biped Robot," from researchers at Chung Yuan Christian University (Taiwan) and Ateneo de Manila University (Philippines). Abstract: "Recently, much research has focused on the design of biped robots with stable and smooth walking ability, identical to human bein... » read more

Computational SRAM (C-SRAM) Solution Combining In- and Near-Memory Computing Approaches


New academic paper titled "Towards a Truly Integrated Vector Processing Unit for Memory-bound Applications Based on a Cost-competitive Computational SRAM Design Solution", from researchers at Univ. Grenoble Alpes, CEA-LIST. Abstract "This article presents Computational SRAM (C-SRAM) solution combining In- and Near-Memory Computing approaches. It allows performing arithmetic, logic, and co... » read more

RISC-V: Advanced Virtual Prototyping Solutions


New technical paper titled "Advanced virtual prototyping for cyber-physical systems using RISC-V: implementation, verification and challenges" from researchers at Institute of Computer Science, University of Bremen and Cyber-Physical Systems, DFKI GmbH. Abstract "Virtual prototypes (VPs) are crucial in today’s design flow. VPs are predominantly created in SystemC transaction-level modelin... » read more

Design of a Mixed-signal ASIC for the front-end electronics of ionisation chambers


New technical paper titled "An Ultra Low Current Measurement Mixed-Signal ASIC for Radiation Monitoring Using Ionisation Chambers," by researchers at CERN. Abstract "Measurement of total ionizing dose in a radiation field is efficiently carried out by ionisation chambers. The paper details the design of a mixed-signal ASIC for the front-end electronics of ionisation chambers. A single c... » read more

A Methodology for Automatic eFPGA redaction


New academic paper titled "ALICE: An Automatic Design Flow for eFPGA Redaction" from researchers at Politecnico di Milano, New York University, University of Calgary, and the University of Utah. Abstract "Fabricating an integrated circuit is becoming unaffordable for many semiconductor design houses. Outsourcing the fabrication to a third-party foundry requires methods to protect the intell... » read more

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