category: Design & Verification

category: IoT, Security & Automotive

Merging Power and Arithmetic Optimization Via Datapath Rewriting (Intel, Imperial College London)
By Technical Paper Link - 19 Apr, 2024 - Comments: 0

A new technical paper titled "Combining Power and Arithmetic Optimization via Datapath Rewriting" was published by researchers at Intel Corporation and Imperial College London. Abstract: "Industrial datapath designers consider dynamic power consumption to be a key metric. Arithmetic circuits contribute a major component of total chip power consumption and are therefore a common target for p... » read more

Feasibility and Potential of Quantum Computing For a Typical EDA Optimization Problem
By Technical Paper Link - 16 Apr, 2024 - Comments: 0

A new technical paper titled "QCEDA: Using Quantum Computers for EDA" was published by researchers at Fraunhofer IESE, RPTU Kaiserslautern, DLR (Germany), and OTH Regensburg. Abstract "The field of Electronic Design Automation (EDA) is crucial for microelectronics, but the increasing complexity of Integrated Circuits (ICs) poses challenges for conventional EDA: Corresponding problems are of... » read more

Hardware Fuzzer Utilizing LLMs
By Technical Paper Link - 12 Apr, 2024 - Comments: 0

A new technical paper titled "Beyond Random Inputs: A Novel ML-Based Hardware Fuzzing" was published by researchers at TU Darmstadt and Texas A&M University. Abstract "Modern computing systems heavily rely on hardware as the root of trust. However, their increasing complexity has given rise to security-critical vulnerabilities that cross-layer at-tacks can exploit. Traditional hardware ... » read more

Comparison Of The Meta Modeling Approach With HGLs
By Technical Paper Link - 09 Apr, 2024 - Comments: 0

A new technical paper titled "The Argument for Meta-Modeling-Based Approaches to Hardware Generation Languages" was published by researchers at Infineon Technologies and TU Munich. Abstract "The rapid evolution of Integrated Circuit (IC) development necessitates innovative methodologies such as code generation to manage complexity and increase productivity. Using the right methodology for g... » read more

Scalable Verification of Memory Consistency (Purdue University)
By Technical Paper Link - 06 Apr, 2024 - Comments: 0

A new technical paper titled "QED: Scalable Verification of Hardware Memory Consistency" was published by researchers at Purdue University. Abstract "Memory consistency model (MCM) issues in out-of-order-issue microprocessor-based shared-memory systems are notoriously non-intuitive and a source of hardware design bugs. Prior hardware verification work is limited to in-order-issue processors... » read more

Power Sub-Mesh Construction To Mitigate IR Drop And Minimize Routing Overhead (Intel)
By Technical Paper Link - 02 Apr, 2024 - Comments: 0

A new technical paper titled "Power Sub-Mesh Construction in Multiple Power Domain Design with IR Drop and Routability Optimization" was published by researchers at Intel Corporation and National Taiwan University. Abstract: "Multiple power domain design is prevalent for achieving aggressive power savings. In such design, power delivery to cross-domain cells poses a tough challenge at adv... » read more

Verifying Hardware CWEs in RTL Designs Generated by GenAI
By Technical Paper Link - 27 Mar, 2024 - Comments: 0

A new technical paper titled "All Artificial, Less Intelligence: GenAI through the Lens of Formal Verification" was published by researchers at Infineon Technologies. Abstract "Modern hardware designs have grown increasingly efficient and complex. However, they are often susceptible to Common Weakness Enumerations (CWEs). This paper is focused on the formal verification of CWEs in a dataset... » read more

HW Implementation of Memristive ANNs
By Technical Paper Link - 22 Mar, 2024 - Comments: 0

A new technical paper titled "Hardware implementation of memristor-based artificial neural networks" was published by KAUST, Universitat Autònoma de Barcelona, IBM Research, USC, University of Michigan and others. Abstract: "Artificial Intelligence (AI) is currently experiencing a bloom driven by deep learning (DL) techniques, which rely on networks of connected simple computing units oper... » read more

Transformer Model Based Clustering Methodology For Standard Cell Layout Automation (Nvidia)
By Technical Paper Link - 19 Mar, 2024 - Comments: 0

A new technical paper titled "Novel Transformer Model Based Clustering Method for Standard Cell Design Automation" was published by researchers at Nvidia. Abstract "Standard cells are essential components of modern digital circuit designs. With process technologies advancing beyond 5nm, more routability issues have arisen due to the decreasing number of routing tracks (RTs), increasing numb... » read more

Predicting Warpage in Different Types of IC Stacks At Early Stage Of Package Design
By Technical Paper Link - 15 Mar, 2024 - Comments: 0

A new technical paper titled "Warpage Study by Employing an Advanced Simulation Methodology for Assessing Chip Package Interaction Effects" was published by researchers at Siemens EDA, D2S, and Univ. Grenoble Alpes, CEA, Leti. Abstract: "A physics-based multi-scale simulation methodology that analyses die stress variations generated by package fabrication is employed for warpage study. The ... » read more

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