category: Design & Verification

category: IoT, Security & Automotive

NVMs: In-Memory Fine-Grained Integrity Verification Technique (Intel Labs, IISc)
By Technical Paper Link - 16 Jul, 2024 - Comments: 0

A new technical paper titled "iMIV: in-Memory Integrity Verification for NVM" was published by researchers at Intel Labs and Indian Institute of Science (IISc), Bengaluru. Abstract "Non-volatile Memory (NVM) could bridge the gap between memory and storage. However, NVMs are susceptible to data remanence attacks. Thus, multiple security metadata must persist along with the data to protect th... » read more

RTL Optimization Via Verified E-Graph Rewriting (Intel, Imperial College London)
By Technical Paper Link - 08 Jul, 2024 - Comments: 0

A technical paper titled “ROVER: RTL Optimization via Verified E-Graph Rewriting” was published by researchers at Intel Corporation and Imperial College London. Abstract: "Manual RTL design and optimization remains prevalent across the semiconductor industry because commercial logic and high-level synthesis tools are unable to match human designs. Our experience in industrial datapath des... » read more

Lower Energy, High Performance LLM on FPGA Without Matrix Multiplication
By Technical Paper Link - 27 Jun, 2024 - Comments: 0

A new technical paper titled "Scalable MatMul-free Language Modeling" was published by UC Santa Cruz, Soochow University, UC Davis, and LuxiTech. Abstract "Matrix multiplication (MatMul) typically dominates the overall computational cost of large language models (LLMs). This cost only grows as LLMs scale to larger embedding dimensions and context lengths. In this work, we show that MatMul... » read more

Overview of Test Strategies for 3DICs
By Technical Paper Link - 26 Jun, 2024 - Comments: 0

A new technical paper titled "Design-for-Test Solutions for 3D Integrated Circuits" was published by researchers at Duke University, Arizona State University, and NVIDIA. Abstract: "As Moore's Law approaches its limits, 3D integrated circuits (ICs) have emerged as promising alternatives to conventional scaling methodologies. However, the benefits of 3D integration in terms of lower power co... » read more

Thermoelectric Active Cooling Hot Spots in Chips
By Technical Paper Link - 26 Jun, 2024 - Comments: 0

A technical paper titled “Thermoelectric active cooling for transient hot spots in microprocessors” was published by researchers at the University of Pittsburgh and Carnegie Mellon University. Abstract: "Modern microprocessor performance is limited by local hot spots induced at high frequency by busy integrated circuit elements such as the clock generator. Locally embedded thermoelectric ... » read more

Using Formal Verification To Evaluate The HW Reliability Of A RISC-V Ibex Core In The Presence Of Soft Errors
By Technical Paper Link - 31 May, 2024 - Comments: 0

A technical paper titled “Using Formal Verification to Evaluate Single Event Upsets in a RISC-V Core” was published by researchers at University of Southampton. Abstract: "Reliability has been a major concern in embedded systems. Higher transistor density and lower voltage supply increase the vulnerability of embedded systems to soft errors. A Single Event Upset (SEU), which is also calle... » read more

Competitive Open-Source EDA Tools
By Technical Paper Link - 19 May, 2024 - Comments: 0

A technical paper titled “Basilisk: Achieving Competitive Performance with Open EDA Tools on an Open-Source Linux-Capable RISC-V SoC” was published by researchers at ETH Zurich and University of Bologna. Abstract: "We introduce Basilisk, an optimized application-specific integrated circuit (ASIC) implementation and design flow building on the end-to-end open-source Iguana system-on-chip (... » read more

Leveraging LLMs To Explain EDA Synthesis Errors And Help Train New Engineers 
By Technical Paper Link - 08 May, 2024 - Comments: 0

A technical paper titled “Explaining EDA synthesis errors with LLMs” was published by researchers at University of New South Wales and University of Calgary. Abstract: "Training new engineers in digital design is a challenge, particularly when it comes to teaching the complex electronic design automation (EDA) tooling used in this domain. Learners will typically deploy designs in the Veri... » read more

Thermal Crosstalk Modelling And Compensation Methods for Programmable Photonic ICs (TU Denmark, iPronics)
By Technical Paper Link - 07 May, 2024 - Comments: 0

A technical paper titled “Thermal Crosstalk Modelling and Compensation Methods for Programmable Photonic Integrated Circuits” was published by researchers at the Technical University of Denmark and iPronics Programmable Photonics. Abstract: "Photonic integrated circuits play an important role in the field of optical computing, promising faster and more energy-efficient operations compared... » read more

A Design And Benchmarking Study Of CAM At 7nm In The Context Of Similarity Search Applications (Georgia Tech)
By Technical Paper Link - 07 May, 2024 - Comments: 0

A technical paper titled “Cross-layer Modeling and Design of Content Addressable Memories in Advanced Technology Nodes for Similarity Search” was published by researchers at the Georgia Institute of Technology. Abstract: "In this paper we present a comprehensive design and benchmarking study of Content Addressable Memory (CAM) at the 7nm technology node in the context of similarity search... » read more

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