category: Design & Verification

category: IoT, Security & Automotive

An Evaluation of Quantum Algorithms On Classical Hardware Using The CuQuantum Framework
By Technical Paper Link - 07 Jun, 2023 - Comments: 0

A technical paper titled “Simulating Noisy Quantum Circuits for Cryptographic Algorithms” was published by researchers at Virginia Tech. Abstract: "The emergence of noisy intermediate-scale quantum (NISQ) computers has important consequences for cryptographic algorithms. It is theoretically well-established that key algorithms used in cybersecurity are vulnerable to quantum computers due ... » read more

Nanosheet GAAFETs: Compact Modeling (Politecnico di Torino)
By Technical Paper Link - 07 Jun, 2023 - Comments: 0

A technical paper titled “NS-GAAFET Compact Modeling: Technological Challenges in Sub-3-nm Circuit Performance” was published by researchers at Politecnico di Torino. Abstract: "NanoSheet-Gate-All-Around-FETs (NS-GAAFETs) are commonly recognized as the future technology to push the digital node scaling into the sub-3 nm range. NS-GAAFETs are expected to replace FinFETs in a few years, as ... » read more

3DICs: Legalizer Techniques For Better Routing Quality, Fewer DRVs, And Reduced Total Slack With Negligible Runtime Impact
By Technical Paper Link - 07 Jun, 2023 - Comments: 0

A technical paper titled “On Legalization of Die Bonding Bumps and Pads for 3D ICs” was published by researchers at the Georgia Institute of Technology, NVIDIA Corporation, and the University of Bremen. Abstract "State-of-the-art 3D IC Place-and-Route flows were designed with older technology nodes and aggressive bonding pitch assumptions. As a result, these flows fail to honor the widt... » read more

Multi-Rate Discrete-Time Modeling Approach Of A Power Hardware-in-the-Loop Setup (Karlsruhe Institute of Technology)
By Technical Paper Link - 07 Jun, 2023 - Comments: 0

A technical paper titled “Multi-rate Discrete Domain Modeling of Power Hardware-in-the-Loop Setups” was published by researchers at the Institute for Technical Physics, Karlsruhe Institute of Technology, Karlsruhe, Germany. Abstract: "Power Hardware-in-the-Loop (PHIL) facilitates the testing of novel power engineering solutions in the lab, allowing a flexible testing environment while kee... » read more

Issues and Opportunities in Using LLMs for Hardware Design
By Technical Paper Link - 01 Jun, 2023 - Comments: 0

A technical paper titled "Chip-Chat: Challenges and Opportunities in Conversational Hardware Design" was published by researchers at NYU and University of New South Wales. Abstract "Modern hardware design starts with specifications provided in natural language. These are then translated by hardware engineers into appropriate Hardware Description Languages (HDLs) such as Verilog before syn... » read more

Non-Traditional Design of Dynamic Logic Gates and Circuits with FDSOI FETs
By Technical Paper Link - 19 May, 2023 - Comments: 1

A new technical paper titled "Non-Traditional Design of Dynamic Logics using FDSOI for Ultra-Efficient Computing" was published by researchers at University of Stuttgart, UC Berkeley, Indian Institute of Technology Kanpur, and TU Munich, with funding by the German Research Foundation. Abstract "In this paper, we propose a non-traditional design of dynamic logic circuits using Fully-Deplet... » read more

RL-Guided Detailed Routing Framework for Advanced Custom Circuits
By Technical Paper Link - 19 May, 2023 - Comments: 0

A technical paper titled "Reinforcement Learning Guided Detailed Routing for Custom Circuits" was published by researchers at UT Austin, Princeton University, and NVIDIA. "This paper presents a novel detailed routing framework for custom circuits that leverages deep reinforcement learning to optimize routing patterns while considering custom routing constraints and industrial design rules. C... » read more

Edge HW-SW Co-Design Platform Integrating RISC-V And HW Accelerators
By Technical Paper Link - 16 May, 2023 - Comments: 0

A new technical paper titled "EigenEdge: Real-Time Software Execution at the Edge with RISC-V and Hardware Accelerators" was published by researchers at Columbia University. "We introduce a hardware/software co-design approach that combines software applications designed with Eigen, a powerful open-source C++ library that abstracts linear-algebra workloads, and real-time execution on heterog... » read more

Server Design With Pin-Efficient CXL Interface (Georgia Tech)
By Technical Paper Link - 10 May, 2023 - Comments: 0

A new technical paper titled "A Case for CXL-Centric Server Processors" was written by researchers at Georgia Tech. Abstract: "The memory system is a major performance determinant for server processors. Ever-growing core counts and datasets demand higher bandwidth and capacity as well as lower latency from the memory system. To keep up with growing demands, DDR--the dominant processor inter... » read more

Performance Of Analog In-Memory Computing On Imaging Problems
By Technical Paper Link - 09 May, 2023 - Comments: 0

A technical paper titled "Accelerating AI Using Next-Generation Hardware: Possibilities and Challenges With Analog In-Memory Computing" was published by researchers at Lund University and Ericsson Research. Abstract "Future generations of computing systems need to continue increasing processing speed and energy efficiency in order to meet the growing workload requirements under stringent en... » read more

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