category: Design & Verification

category: IoT, Security & Automotive

Circuit Layout-Level Hardware Trojan Detection
By Technical Paper Link - 09 May, 2023 - Comments: 0

A new technical paper titled "A Needle in the Haystack: Inspecting Circuit Layout to Identify Hardware Trojans" was published by researchers at The University of Texas at Dallas and Qualcomm. Abstract "Distributed integrated circuit (IC) supply chain has resulted in a myriad of security vulnerabilities including that of hardware Trojan (HT). An HT can perform malicious modifications on an I... » read more

Recent Developments in Neuromorphic Computing, Focusing on Hardware Design and Reliability
By Technical Paper Link - 08 May, 2023 - Comments: 0

A new technical paper titled "Special Session: Neuromorphic hardware design and reliability from traditional CMOS to emerging technologies" was published by researchers at Univ. Lyon, Ecole Centrale de Lyon, Univ. Grenoble Alpes, Hewlett Packard Labs, CEA-LETI, and Politecnico di Torino. Abstract "The field of neuromorphic computing has been rapidly evolving in recent years, with an incre... » read more

Toolbox For Designing Heterogeneous Quantum Systems
By Technical Paper Link - 08 May, 2023 - Comments: 0

A new technical paper titled "Microarchitectures for Heterogeneous Superconducting Quantum Computers" was published by researcher at: Pacific Northwest National Laboratory, Princeton University, University of Chicago, Rutgers University, MIT, Brookhaven National Laboratory, and Infleqtion. Abstract: "Noisy Intermediate-Scale Quantum Computing (NISQ) has dominated headlines in recent years, ... » read more

NIST Releases “Vision And Strategy for the National Semiconductor Technology Center”
By Technical Paper Link - 05 May, 2023 - Comments: 0

A paper titled "A Vision and Strategy for the National Semiconductor Technology Center" was published by the U.S. Department of Commerce’s National Institute of Standards and Technology (NIST). The paper describes how the NSTC (National Semiconductor Technology Center) will develop and safeguard chips and technologies of the future. “The NSTC will be an ambitious public-private consortiu... » read more

Attestation Scheme Monitoring The Prover Using Hardware Security Module Connected To Its System Bus (Oxford)
By Technical Paper Link - 05 May, 2023 - Comments: 0

A technical paper titled "Hardware-assisted remote attestation design for critical embedded systems" was published by researchers at University of Oxford. Abstract (excerpt) "To reveal attack scenarios exploiting the memory regions and time windows left unattested, we propose an attestation scheme that can continuously monitor both static and dynamic memory regions with better spatial and t... » read more

ML-Based Third-Party IP Trust Verification Framework (U. of Florida, U. of Kansas)
By Technical Paper Link - 01 May, 2023 - Comments: 0

A technical paper titled "Hardware IP Assurance against Trojan Attacks with Machine Learning and Post-processing" was published by researchers at University of Florida and University of Kansas. Abstract: "System-on-chip (SoC) developers increasingly rely on pre-verified hardware intellectual property (IP) blocks often acquired from untrusted third-party vendors. These IPs might contain hidd... » read more

EPFL’s Open Source Single-Core RISC-V Microcontroller for Edge Computing
By Technical Paper Link - 30 Apr, 2023 - Comments: 0

A new technical paper titled "X-HEEP: An Open-Source, Configurable and Extendible RISC-V Microcontroller" was published by researchers at Ecole Polytechnique Fédérale de Lausanne (EPFL). Abstract: "In this work, we present eXtendible Heterogeneous Energy-Efficient Platform (X-HEEP), a configurable and extendible single-core RISC-V-based ultra-low-power microcontroller. X-HEEP can be used ... » read more

Hardware-Accelerated RTL Simulator
By Technical Paper Link - 26 Apr, 2023 - Comments: 0

A technical paper titled "Manticore: Hardware-Accelerated RTL Simulation with Static Bulk-Synchronous Parallelism" was published by researchers at EPFL, University of Tokyo, Sharif University, and Indian Institute of Technology. Abstract "The demise of Moore's Law and Dennard Scaling has revived interest in specialized computer architectures and accelerators. Verification and testing of thi... » read more

Information flow policies for NVM Technologies
By Technical Paper Link - 26 Apr, 2023 - Comments: 0

A new technical paper titled "Automated Information Flow Analysis for Integrated Computing-in-Memory Modules" was published by researchers at RWTH Aachen University. Abstract: "Novel non-volatile memory (NVM) technologies offer high-speed and high-density data storage. In addition, they overcome the von Neumann bottleneck by enabling computing-in-memory (CIM). Various computer architectures... » read more

Data-Centric Reconfigurable Array Chiplets (Princeton)
By Technical Paper Link - 21 Apr, 2023 - Comments: 0

A technical paper titled "Massive Data-Centric Parallelism in the Chiplet Era" was published by researchers at Princeton University. Abstract: "Traditionally, massively parallel applications are executed on distributed systems, where computing nodes are distant enough that the parallelization schemes must minimize communication and synchronization to achieve scalability. Mapping communica... » read more

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