A Lightweight Scan Instrumentation For Enhancing The Post-Silicon Test Efficiency in ICs (U. of Florida)


A technical paper titled "Enhancing Test Efficiency through Automated ATPG-Aware Lightweight Scan Instrumentation" was published by researchers at University of Florida. Abstract "Scan-based Design-for-Testability (DFT) measures are prevalent in modern digital integrated circuits to achieve high test quality at low hardware cost. With the advent of 3D heterogeneous integration and chiplet-b... » read more

Role of Josephson Junctions In Propelling Quantum Technologies Forward (LBNL, UC Berkeley, et al.)


A new technical paper titled "Josephson Junctions in the Age of Quantum Discovery" was published by researchers at Lawrence Berkeley National Laboratory, UC Berkeley, Gwangju Institute of Science and Technology, Korea University, Max Planck and Anyon Computing. Abstract "The unique combination of energy conservation and nonlinear behavior exhibited by Josephson junctions has driven transfor... » read more

Optimization Approach For The Dispensing of Thermal Interface Material (KIT, Robert Bosch)


A new technical paper titled "TIMtrace: Coverage Path Planning for Thermal Interface Materials" was published by researchers at Karlsruhe Institute of Technology (KIT) and Robert Bosch GmbH. Abstract "Thermal Interface Materials are used to transfer heat from a semiconductor to a heatsink. They are applied along a dispense path onto the semiconductor and spread over its entire surface once ... » read more

Open-Source And Royalty-Free Confidential Computing For Embedded RISC-V Systems (IBM, Max Planck)


A new technical paper titled "ACE: Confidential Computing for Embedded RISC-V Systems" was published by researchers at IBM Research, IBM T.J. Watson Research Center, Max Planck Institute for Software Systems (MPI-SWS). Abstract "Confidential computing plays an important role in isolating sensitive applications from the vast amount of untrusted code commonly found in the modern cloud. We a... » read more

Energy-Aware DL: The Interplay Between NN Efficiency And Hardware Constraints (Imperial College London, Cambridge)


A new technical paper titled "Energy-Aware Deep Learning on Resource-Constrained Hardware" was published by researchers at Imperial College London and University of Cambridge. Abstract "The use of deep learning (DL) on Internet of Things (IoT) and mobile devices offers numerous advantages over cloud-based processing. However, such devices face substantial energy constraints to prolong batte... » read more

Customizing A LLM Model For VHDL Design of High-Performance MPUs (IBM)


A new technical paper titled "Customizing a Large Language Model for VHDL Design of High-Performance Microprocessors" was published by researchers at IBM. Abstract "The use of Large Language Models (LLMs) in hardware design has taken off in recent years, principally through its incorporation in tools that increase chip designer productivity. There has been considerable discussion about the ... » read more

Floorplanning Method For Reducing Thermally-Induced Structural Stress In Chiplet Packages (Penn State, Intel, ASU et al.)


A new technical paper titled "STAMP-2.5D: Structural and Thermal Aware Methodology for Placement in 2.5D Integration" was published by researchers at Pennsylvania State University, Intel, Arizona State University and University of Notre Dame. Abstract "Chiplet-based architectures and advanced packaging has emerged as transformative approaches in semiconductor design. While conventional ph... » read more

Effects Of Hardware Prefetchers For Scientific Application Kernels Running on High-End Processors


A new technical paper titled "Memory Prefetching Evaluation of Scientific Applications on A Modern HPC Arm-based Processor" was published by researchers at Jülich Supercomputing Centre and KTH Royal Institute of Technology. Abstract "Memory prefetching is a well-known technique for mitigating the negative impact of memory access latencies on memory bandwidth. This problem has become more p... » read more

CFETs: Reliability of Complementary Field-Effect Transistors (TU Munich, IIT)


A technical paper titled "CFET Beyond 3 nm: SRAM Reliability under Design-Time and Run-Time Variability" was published by researchers at TU Munich and IIT Kanpur. Abstract "This work investigates the reliability of complementary field-effect transistors (CFETs) by addressing both design-time variability arising from process variations and run-time variability due to temperature and aging ef... » read more

Embedded GPU: An Open-Source And Configurable RISC-V GPU Platform for TinyAI Devices (EPFL)


A new technical paper titled "e-GPU: An Open-Source and Configurable RISC-V Graphic Processing Unit for TinyAI Applications" was published by researchers at EPFL. Abstract "Graphics processing units (GPUs) excel at parallel processing, but remain largely unexplored in ultra-low-power edge devices (TinyAI) due to their power and area limitations, as well as the lack of suitable programming... » read more

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