category: Design & Verification

category: IoT, Security & Automotive

Characteristics and Potential HW Architectures for Neuro-Symbolic AI
By Technical Paper Link - 23 Sep, 2024 - Comments: 0

A new technical paper titled "Towards Efficient Neuro-Symbolic AI: From Workload Characterization to Hardware Architecture" was published by researchers at Georgia Tech, UC Berkeley, and IBM Research. Abstract: "The remarkable advancements in artificial intelligence (AI), primarily driven by deep neural networks, are facing challenges surrounding unsustainable computational trajectories, li... » read more

3D IC Partitioning and Placement Method That Optimizes For Critical Paths (POSTECH)
By Technical Paper Link - 12 Sep, 2024 - Comments: 0

A new technical paper titled "TA3D: Timing-Aware 3D IC Partitioning and Placement by Optimizing the Critical Path" was published by researchers at Pohang University of Science and Technology and Baum Design Systems. Abstract "In the face of challenges posed by semiconductor scaling, 3D integration technology has emerged as a crucial solution to overcome the constraints of traditional 2D I... » read more

Hardware-Side-Channel Leakage Contracts That Account For Glitches and Transitions (TU Graz)
By Technical Paper Link - 10 Sep, 2024 - Comments: 0

A new technical paper titled "Closing the Gap: Leakage Contracts for Processors with Transitions and Glitches" was published by researchers at Graz University of Technology. Abstract "Security verification of masked software implementations of cryptographic algorithms must account for microarchitectural side-effects of CPUs. Leakage contracts were proposed to provide a formal separation bet... » read more

GPU Microarchitecture Integrating Dedicated Matrix Units At The Cluster Level (UC Berkeley)
By Technical Paper Link - 27 Aug, 2024 - Comments: 0

A new technical paper titled "Virgo: Cluster-level Matrix Unit Integration in GPUs for Scalability and Energy Efficiency" was published by UC Berkeley. Abstract "Modern GPUs incorporate specialized matrix units such as Tensor Cores to accelerate GEMM operations central to deep learning workloads. However, existing matrix unit designs are tightly coupled to the SIMT core, limiting the size a... » read more

LLMs In The High-Level Synthesis Design Flow
By Technical Paper Link - 27 Aug, 2024 - Comments: 0

A new technical paper titled "Are LLMs Any Good for High-Level Synthesis?" was published by researchers at University of Arizona. Abstract "The increasing complexity and demand for faster, energy-efficient hardware designs necessitate innovative High-Level Synthesis (HLS) methodologies. This paper explores the potential of Large Language Models (LLMs) to streamline or replace the HLS proces... » read more

5 Novel Layout Design Methodologies For The 3nm Nanosheet FET Library (Samsung, KNU)
By Technical Paper Link - 13 Aug, 2024 - Comments: 0

A new technical paper titled "Design Technology Co-Optimization and Time-Efficient Verification for Enhanced Pin Accessibility in the Post-3-nm Node" was published by researchers at Samsung Electronics and Kyungpook National University (KNU). Abstract: "As the technology nodes approach 3 nm and beyond, nanosheet FETs (NSFETs) are replacing FinFETs. However, despite the migration of devices ... » read more

A Hybrid ECO Detailed Placement Flow for Mitigating Dynamic IR Drop (UC San Diego)
By Technical Paper Link - 01 Aug, 2024 - Comments: 0

A new technical paper titled "A Hybrid ECO Detailed Placement Flow for Improved Reduction of Dynamic IR Drop" was published by researchers at UC San Diego. Abstract: "With advanced semiconductor technology progressing well into sub-7nm scale, voltage drop has become an increasingly challenging issue. As a result, there has been extensive research focused on predicting and mitigating dynam... » read more

Using Diffusion Models to Generate Chip Placements (UC Berkeley)
By Technical Paper Link - 27 Jul, 2024 - Comments: 0

A technical paper titled “Chip Placement with Diffusion” was published by researchers at UC Berkeley. Abstract: "Macro placement is a vital step in digital circuit design that defines the physical location of large collections of components, known as macros, on a 2-dimensional chip. The physical layout obtained during placement determines key performance metrics of the chip, such as power... » read more

Formal Verification of Security Properties On RTL Designs
By Technical Paper Link - 27 Jul, 2024 - Comments: 0

A technical paper titled “RTL Verification for Secure Speculation Using Contract Shadow Logic” was published by researchers at Princeton University, MIT CSAIL, and EPFL. Abstract: "Modern out-of-order processors face speculative execution attacks. Despite various proposed software and hardware mitigations to prevent such attacks, new attacks keep arising from unknown vulnerabilities. Thus... » read more

NVMs: In-Memory Fine-Grained Integrity Verification Technique (Intel Labs, IISc)
By Technical Paper Link - 16 Jul, 2024 - Comments: 0

A new technical paper titled "iMIV: in-Memory Integrity Verification for NVM" was published by researchers at Intel Labs and Indian Institute of Science (IISc), Bengaluru. Abstract "Non-volatile Memory (NVM) could bridge the gap between memory and storage. However, NVMs are susceptible to data remanence attacks. Thus, multiple security metadata must persist along with the data to protect th... » read more

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