category: Design & Verification

category: IoT, Security & Automotive

Scalable And Energy Efficient Solution for Hardware-Based ANNs (KAUST, NUS)
By Technical Paper Link - 30 Mar, 2025 - Comments: 0

A new technical paper titled "Synaptic and neural behaviours in a standard silicon transistor" was published by researchers at KAUST and National University of Singapore. Abstract "Hardware implementations of artificial neural networks (ANNs)—the most advanced of which are made of millions of electronic neurons interconnected by hundreds of millions of electronic synapses—have achieved ... » read more

GPU Analysis Identifying Performance Bottlenecks That Cause Throughput Plateaus In Large-Batch Inference
By Technical Paper Link - 30 Mar, 2025 - Comments: 1

A new technical paper titled "Mind the Memory Gap: Unveiling GPU Bottlenecks in Large-Batch LLM Inference" was published by researchers at Barcelona Supercomputing Center, Universitat Politecnica de Catalunya, and IBM Research. Abstract "Large language models have been widely adopted across different tasks, but their auto-regressive generation nature often leads to inefficient resource util... » read more

Evaluation Tool For The Cost Impacts Of Chiplet-Specific Design Choices
By Technical Paper Link - 25 Mar, 2025 - Comments: 0

A new technical paper titled "CATCH: a Cost Analysis Tool for Co-optimization of chiplet-based Heterogeneous systems" was published by researchers at UCLA, Duke University and Arizona State University. Abstract "With the increasing prevalence of chiplet systems in high-performance computing applications, the number of design options has increased dramatically. Instead of chips defaulting to... » read more

Defect Analysis and Testing Framework For FOWLP Interconnects
By Technical Paper Link - 24 Mar, 2025 - Comments: 0

A new technical paper titled "Defect Analysis and Built-In-Self-Test for Chiplet Interconnects in Fan-out Wafer-Level Packaging" was published by researchers at Arizona State University. Abstract "Fan-out wafer-level packaging (FOWLP) addresses the demand for higher interconnect densities by offering reduced form factor, improved signal integrity, and enhanced performance. However, FOWLP fa... » read more

Design Optimization Techniques To Improve NC-CFET Performance
By Technical Paper Link - 14 Mar, 2025 - Comments: 0

A new technical paper titled "Insights Into Design Optimization of Negative Capacitance Complementary-FET (CFET)" was published by researchers at National Yang Ming Chiao Tung University. Abstract "This work assesses and analyzes negative-capacitance CFETs (NC-CFETs) with metal-ferroelectric-insulator-semiconductor (MFIS) and metal-ferroelectric-metal-insulator-semiconductor (MFMIS) configu... » read more

Multi-Party Computation for Securing Chiplets
By Technical Paper Link - 12 Mar, 2025 - Comments: 0

A new technical paper titled "Garblet: Multi-party Computation for Protecting Chiplet-based Systems" was published by Worcester Polytechnic Institute. Abstract "The introduction of shared computation architectures assembled from heterogeneous chiplets introduces new security threats. Due to the shared logical and physical resources, an untrusted chiplet can act maliciously to surreptitiousl... » read more

A Novel Tier Partitioning Method in 3DIC Placement Optimizing PPA
By Technical Paper Link - 11 Mar, 2025 - Comments: 0

A new technical paper titled "PPA-Aware Tier Partitioning for 3D IC Placement with ILP Formulation" was published by researchers at Seoul National University and Ulsan National Institute of Science and Technology. Abstract "3D ICs are renowned for their potential to enable high-performance and low-power designs by utilizing denser and shorter inter-tier connections. In the physical design f... » read more

Thermal-Aware DSE Framework for 3DICs, With Advanced Cooling Models
By Technical Paper Link - 11 Mar, 2025 - Comments: 0

A new technical paper titled "Cool-3D: An End-to-End Thermal-Aware Framework for Early-Phase Design Space Exploration of Microfluidic-Cooled 3DICs" was published by researchers at University of Michigan, Shanghai Jiao Tong University and University of Virginia. Abstract "The rapid advancement of three-dimensional integrated circuits (3DICs) has heightened the need for early-phase design spa... » read more

Thermally Aware Chiplet Placement Algorithm Based on Automatic Differentiation (MIT, IBM)
By Technical Paper Link - 07 Mar, 2025 - Comments: 0

A new technical paper titled "DiffChip: Thermally Aware Chip Placement with Automatic Differentiation" was published by researchers at MIT and IBM. Abstract "Chiplets are modular integrated circuits that can be combined to form a larger system, offering flexibility and performance enhancements. However, their dense packing often leads to significant thermal management challenges, requiring ... » read more

Field-Coupled Nanocomputing: Scalable And Efficient Post-Layout Optimization (TU Munich)
By Technical Paper Link - 07 Mar, 2025 - Comments: 0

A new technical paper titled "Efficient and Scalable Post-Layout Optimization for Field-coupled Nanotechnologies" was published by researcher at the Technical University of Munich (TUM). Abstract "As conventional computing technologies approach their physical limits, the quest for increased computational power intensifies, heightening interest in post-CMOS technologies. Among these, Field... » read more

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