category: Design & Verification

category: IoT, Security & Automotive

Chiplet Architecture: Scalable and Cost-Efficient Systems for Irregular Applications (Princeton)
By Technical Paper Link - 30 Nov, 2023 - Comments: 0

A new technical paper titled "DCRA: A Distributed Chiplet-based Reconfigurable Architecture for Irregular Applications" was published by researchers at Princeton University. Abstract "In recent years, the growing demand to process large graphs and sparse datasets has led to increased research efforts to develop hardware- and software-based architectural solutions to accelerate them. While... » read more

Chiplets For Generative AI Workloads: Challenges in both HW and SW
By Technical Paper Link - 29 Nov, 2023 - Comments: 0

A new technical paper titled "Challenges and Opportunities to Enable Large-Scale Computing via Heterogeneous Chiplets" was published by researchers at University of Pittsburgh, Lightelligence, and Meta. Abstract "Fast-evolving artificial intelligence (AI) algorithms such as large language models have been driving the ever-increasing computing demands in today's data centers. Heterogeneous c... » read more

LLM Inference On CPUs (Intel)
By Technical Paper Link - 16 Nov, 2023 - Comments: 0

A technical paper titled “Efficient LLM Inference on CPUs” was published by researchers at Intel. Abstract: "Large language models (LLMs) have demonstrated remarkable performance and tremendous potential across a wide range of tasks. However, deploying these models has been challenging due to the astronomical amount of model parameters, which requires a demand for large memory capacity an... » read more

A HIL Methodology For The SoC Development Flow
By Technical Paper Link - 14 Nov, 2023 - Comments: 0

A technical paper titled “Virtual-Peripheral-in-the-Loop : A Hardware-in-the-Loop Strategy to Bridge the VP/RTL Design-Gap” was published by researchers at University of Bremen and German Research Center for Artificial Intelligence (DFKI). Abstract: "Virtual Prototypes act as an executable specification model, offering a unified behavior reference model for SW and HW engineers. However, b... » read more

Verifying The Integrity Of ICs Based On Their Electromagnetic (EM) Near-Field Emissions
By Technical Paper Link - 14 Nov, 2023 - Comments: 0

A technical paper titled “Contact-Less Integrity Verification of Microelectronics Using Near-Field EM Analysis” was published by researchers at University of Florida and Brookhaven National Laboratory. Abstract: "Modern microelectronics life-cycle and supply chain ecosystem bring multiple untrusted entities, which can compromise their integrity. A major integrity issue of microelectronics... » read more

Applications Of Large Language Models For Industrial Chip Design (NVIDIA)
By Technical Paper Link - 10 Nov, 2023 - Comments: 0

A technical paper titled “ChipNeMo: Domain-Adapted LLMs for Chip Design” was published by researchers at NVIDIA. Abstract: "ChipNeMo aims to explore the applications of large language models (LLMs) for industrial chip design. Instead of directly deploying off-the-shelf commercial or open-source LLMs, we instead adopt the following domain adaptation techniques: custom tokenizers, domain-ad... » read more

Improving The Retention Characteristics Of 3D NAND Flash Memories
By Technical Paper Link - 31 Oct, 2023 - Comments: 0

A technical paper titled “3D NAND Flash Memory Cell Current and Interference Characteristics Improvement With Multiple Dielectric Spacer” was published by researchers at Myongji University, Soongsil University, and Seoul National University. Abstract: "To achieve high density, the spacer length of three dimensional (3D) NAND device has been scaled down. When the program/erase cycle repeat... » read more

A New Architecture And Verification Approach For Hardware Security Modules
By Technical Paper Link - 31 Oct, 2023 - Comments: 0

A technical paper titled “The K2 Architecture for Trustworthy Hardware Security Modules” was published by researchers at MIT Computer Science and Artificial Intelligence Laboratory (CSAIL) and New York University. Abstract: "K2 is a new architecture and verification approach for hardware security modules (HSMs). The K2 architecture's rigid separation between I/O, storage, and computation ... » read more

Potentials And Issues Of Designing Fault-Tolerant Hardware Acceleration For Edge-Computing Devices
By Technical Paper Link - 31 Oct, 2023 - Comments: 0

A technical paper titled “Fault-Tolerant Hardware Acceleration for High-Performance Edge-Computing Nodes” was published by researchers at University of Rome. Abstract: "High-performance embedded systems with powerful processors, specialized hardware accelerators, and advanced software techniques are all key technologies driving the growth of the IoT. By combining hardware and software tec... » read more

Shallow Clock Tree Pre-Estimation for Designing Clock Tree Synthesizable Verilog RTLs (Kyungpook National University)
By Technical Paper Link - 31 Oct, 2023 - Comments: 0

A technical paper titled “Shallow Clock Tree Pre-Estimation for Designing Clock Tree Synthesizable Verilog RTLs” was published by researchers at Kyungpook National University. Abstract: "Clock tree synthesis (CTS) is an important process in determining overall chip timing and power consumption. The CTS is also a time-consuming process for checking the clock tree. If the chip design and sp... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy