3D Integration And Test Results From TSV-Processed Chips (CERN et al.)


A new technical paper titled "3D integration of pixel readout chips using Through-Silicon-Vias" was published by researchers at CERN, IZM Fraunhofer and University of Geneva. Abstract "Particle tracking and imaging detectors are becoming increasingly complex, driven by demands for densely integrated functionality and maximal sensitive area. These challenging requirements can be met using 3D... » read more

Schottky Barrier Transistors: Status, Challenges and Modeling Tools


A technical paper titled "Roadmap for Schottky barrier transistors" was published by researchers at University of Surrey, Namlab gGmbH, Forschungszentrum Jülich (FZJ), et al. Abstract "In this roadmap we consider the status and challenges of technologies that use the properties of a rectifying metal-semiconductor interface, known as a Schottky barrier (SB), as an asset for device functio... » read more

2D Ferroelectric Field-Effect Transistors (Penn State, U. of Minnesota)


A new technical paper titled "Multifunctional 2D FETs exploiting incipient ferroelectricity in freestanding SrTiO3 nanomembranes at sub-ambient temperatures" was published by researchers at Penn State University and University of Minnesota. Abstract "Incipient ferroelectricity bridges traditional dielectrics and true ferroelectrics, enabling advanced electronic and memory devices. Firstly... » read more

Advancements in SOT-MRAM Device Development (imec)


A technical paper titled "Recent progress in spin-orbit torque magnetic random-access memory" was recently published by imec. Abstract "Spin-orbit torque magnetic random-access memory (SOT-MRAM) offers promise for fast operation and high endurance but faces challenges such as low switching current, reliable field free switching, and back-end of line manufacturing processes. We review rece... » read more

Ammonia Plasma Surface Treatment for Improved Cu–Cu Bonding Reliability


A new technical paper titled "Ammonia Plasma Surface Treatment for Enhanced Cu–Cu Bonding Reliability for Advanced Packaging Interconnection" was published by researchers at Myongji University. Abstract "With the emergence of 3D stacked semiconductor products, such as high-bandwidth memory, bonding-interface reliability cannot be overemphasized. The condition of the surface interface befo... » read more

Wafer Bin Map Defect Classification Using Semi-Supervised Learning


A new technical paper titled "Semi-Supervised Learning with Wafer-Specific Augmentations for Wafer Defect Classification" was published by researchers at Korea University. Abstract "Semi-supervised learning (SSL) models, which leverage both labeled and unlabeled datasets, have been increasingly applied to classify wafer bin map patterns in semiconductor manufacturing. These models typical... » read more

Promising Materials Beyond Silicon (TI, AIXTRON, imec)


A new technical paper titled "Future materials for beyond Si integrated circuits: a Perspective" was published by researchers at Texas Instruments, AIXTRON SE and imec. Abstract: "The integration of novel materials has been pivotal in advancing Si-based devices ever since Si became the preferred material for transistors, and later, integrated circuits. New materials have rapidly been adopte... » read more

Manipulating Diamond Surface Chemistry By UV Laser Etching (Macquarie Univ., MIT)


A new technical titled "The effects of sub-monolayer laser etching on the chemical and electrical properties of the (100) diamond surface" was published by researchers at Macquarie University and MIT. Abstract "Tailoring the surface chemistry of diamond is critical to a range of applications from quantum science to electronics. It has been recently shown that dosing the diamond surface with... » read more

Patterning Doping On Very Large Monolayer MoS2 (NREL)


A new technical paper titled "Spatially Precise Light-Activated Dedoping in Wafer-Scale MoS2 Films" was published by researchers at National Renewable Energy Laboratory (NREL) and Renewable & Sustainable Energy Institute (RASEI). "In this work, we unravel the mechanism that drives PL* changes of MoS2 monolayers under laser illumination in ambient conditions. We demonstrate the critical ... » read more

Monitor Etch Defects on Dies in the Outer Regions Of The Wafer Using ISR


A technical paper titled "Detection of defective chips from nanostructures with a high-aspect ratio using hyperspectral imaging and deep learning" was published by researchers at Samsung Electronics. Abstract: "We have developed an imaging spectroscopic reflectometry (ISR) method based on hyperspectral imaging and deep learning to detect defects in the bottom region of high-aspect-ratio nan... » read more

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