Design Comparison of SiC MOSFETs for Linear-Mode Operation


Source: US Army Research Lab Authors: Heather O'Brien, Damian Urciuoli, Aderinto Ogunniyi, Brett Hull August 2019 "Abstract: Silicon carbide metal-oxide semiconductor field-effect transistors (MOSFETs) were designed and fabricated for linear-mode applications. The MOSFETs have a chip area of 3.3 ? 3.3 mm and a voltage-blocking rating up to 1200 V. The device design parameters, such as chan... » read more

Investigation and Methods Using Various Release and Thermoplastic Bonding Materials to Reduce Die Shift and Wafer Warpage for eWLB Chip-First Processes


Today's fan-out wafer-level packaging (FOWLP) processes use organic substrates composed of epoxy mold compound (EMC) created using a thermal compression process. EMC wafers are a cost-effective way to achieve lower profile packages without using an inorganic substrate to produce chip packages that are thinner and faster without the need for interposers or through-silicon-vias (TSVs). One approa... » read more

Sacrificial Laser Release Materials For RDL-First Fan-Out Packaging


The semiconductor industry is in a new age where device scaling will not continue to provide the cost reductions or performance improvements at a similar rate to past years when Moore’s law was the guiding principle for IC scaling. The cost of scaling below 7 nm nodes is rising substantially and requires significant investment in capital equipment and R&D spending for next-generation lithogra... » read more

Silicon CMOS Architecture For A Spin-based Quantum Computer


Source: UNSW Sydney Authors: M. Veldhorst (1,2),  H.G.J. Eenink (2,3) , C.H. Yang (2), and A.S. Dzurak (2) 1 Qutech, TU Delft, The Netherlands 2 Centre for Quantum Computation and Communication Technology, School of Electrical Engineering and Telecommunications,UNSW, Sydney, Australia 3 NanoElectronics Group, MESA+ Institute for Nanotechnology,University of Twente, The Netherlands Te... » read more

Overlay Control for Nanoimprint Lithography


Abstract:  Nanoimprint lithography (NIL) is a promising technique for fine-patterning with a lower cost than other lithography techniques such as EUV or immersion with multi-patterning. NIL has the potential of "single" patterning for both line patterns and hole patterns with a half-pitch of less than 20nm. NIL tools for semiconductor manufacturing employ die- by-die alignment syste... » read more

Overlay Control for Nanoimprint Lithography


Abstract: Nanoimprint lithography (NIL) is a promising technique for fine-patterning with a lower cost than other lithography techniques such as EUV or immersion with multi-patterning. NIL has the potential of "single" patterning for both line patterns and hole patterns with a half-pitch of less than 20nm. NIL tools for semiconductor manufacturing employ die- by-die alignment system ... » read more

Adaptive Test With Test Escape Estimation for Mixed-Signal ICs


Abstract: The standard approach in industry for post-manufacturing testing of mixed-signal circuits is to measure the performances that are included in the data sheet. Despite being accurate and straightforward, this approach involves a high test time since there are numerous performances that need to be measured sequentially by switching the circuit into different test configurations. Adapt... » read more

Higher-Than-Ballistic Conduction of Viscous Electron Flows (MIT & Weizmann)


Source: Massachusetts Institute of Technology, Weizmann Institute of Science, Rehovot  Israel Haoyu Guo, Ekin Ilseven, Gregory Falkovich, Leonid Levitov "A new finding by physicists at MIT and in Israel shows that under certain specialized conditions, electrons can speed through a narrow opening in a piece of metal more easily than traditional theory says is possible. This “superball... » read more

What we know after twelve years developing and deploying test data analytics solutions


Abstract: Since 2004, Texas Instruments and Portland State University have collaborated to develop and deploy test data analytical methods for use in a variety of applications, including quality screening, burn-in minimization, high cost test replacement and/or removal, and operations monitoring. In this paper, key findings amassed during this time are summarized. Find the technical paper h... » read more

Sub-Lithographic Patterning Via Tilted Ion Implantation For Scaling Beyond The 7nm Technology Node


Tilted ion implantation (TII) can be used in conjunction with pre-existing masking features on the surface of a substrate to form features with smaller dimensions and smaller pitch. In this paper, the resolution limit of this sub-lithographic patterning approach is examined via experiments as well as Monte Carlo process simulations. TII is shown to be capable of defining features with size belo... » read more

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