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Checkmate: Breaking The Memory Wall With Optimal Tensor Rematerialization


Source: Published on arXiv 10/7/ 2019   Paras Jain Ajay Jain Aniruddha Nrusimha Amir Gholami Pieter Abbeel Kurt Keutzer Ion Stoica Joseph E. Gonzalez A recent paper published on arXiv by a team of UC Berkeley researchers notes that neural networks are increasingly impeded by the limited capacity of on-device GPU memory. The UC Berkeley team uses off-the-shel... » read more

Copy-Row DRAM (CROW) : Substrate for Improving DRAM


Source/Credit: ETH Zurich & Carnegie Mellon University Click here for the technical paper and here for the power point slides » read more

Making high-capacity data caches more efficient


Source: Researchers from MIT, Intel, and ETH Zurich Xiangyao Yu (MIT), Christopher J. Hughes (Intel), Nadathur Satish (Intel) Onur Mutlu (ETH Zurich), Srinivas Devadas (MIT) Technical Paper link MIT News article As the transistor counts in processors have gone up, the relatively slow connection between the processor and main memory has become the chief impediment to improving comp... » read more

Memory Model Verification at the Trisection of Software, Hardware, and ISA (Princeton)


Source: Princeton University, Caroline Trippel, Yatin A. Manerkar, Daniel Lustig*, Michael Pellauer*, Margaret Martonosi *NVIDIA Princeton University researchers have discovered a series of errors in the RISC-V instruction specification that now are leading to changes in the new system, which seeks to facilitate open-source design for computer chips. In testing a technique they created for... » read more