category: Memory

category: IoT, Security & Automotive

Open-Source RISC-V Cores: Analysis Of Scalar and Superscalar Architectures And Out-Of-Order Machines
By Technical Paper Link - 05 Jun, 2025 - Comments: 0

A new technical paper titled "Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution" was published by researchers at ETH Zurich, Università di Bologna and Univ. Grenoble Alpes, Inria. Abstract "Open-source RISC-V cores are increasingly demanded in domains like automotive and space, where achieving high instructions per cycle (IPC) throu... » read more

Hardware-Oriented Analysis of Multi-Head Latent Attention (MLA) in DeepSeek-V3 (KU Leuven)
By Technical Paper Link - 04 Jun, 2025 - Comments: 0

A new technical paper titled "Hardware-Centric Analysis of DeepSeek's Multi-Head Latent Attention" was published by researchers at KU Leuven. Abstract "Multi-Head Latent Attention (MLA), introduced in DeepSeek-V2, improves the efficiency of large language models by projecting query, key, and value tensors into a compact latent space. This architectural change reduces the KV-cache size and s... » read more

V-NAND PUFs (Seoul National University, SK hynix)
By Technical Paper Link - 03 Jun, 2025 - Comments: 0

A new technical paper titled "Concealable physical unclonable functions using vertical NAND flash memory" was published by researchers at Seoul National University and SK hynix. The paper proposes "a concealable PUF using V-NAND flash memory by generating PUF data through weak Gate-Induced-Drain-Leakage (GIDL) erase." Find the technical paper here. June 2025. Park, SH., Koo, RH., Yang,... » read more

Arithmetic Intensity In Decoding: A Hardware-Efficient Perspective (Princeton University)
By Technical Paper Link - 03 Jun, 2025 - Comments: 0

A new technical paper titled "Hardware-Efficient Attention for Fast Decoding" was published by researchers at Princeton University. Abstract "LLM decoding is bottlenecked for large batches and long contexts by loading the key-value (KV) cache from high-bandwidth memory, which inflates per-token latency, while the sequential nature of decoding limits parallelism. We analyze the interplay amo... » read more

SRAM Cell Scaling With Monolithic 3D Integration Of 2D FETs (Penn State)
By Technical Paper Link - 01 Jun, 2025 - Comments: 0

A new technical paper titled "Enabling static random-access memory cell scaling with monolithic 3D integration of 2D field-effect transistors" was published by researchers at The Pennsylvania State University. Abstract "Static Random-Access Memory (SRAM) cells are fundamental in computer architecture, serving crucial roles in cache memory, buffers, and registers due to their high-speed perf... » read more

Transformation Of 2D-ICs Into 3D-ICs Using Shuttle Chips From Multi-Project Wafers (Tohoku University)
By Technical Paper Link - 20 May, 2025 - Comments: 0

A new technical paper titled "Die-Level Transformation of 2D Shuttle Chips into 3D-IC for Advanced Rapid Prototyping using Meta Bonding" was published by researchers at Tohoku University. Abstract "Three-dimensional integrated circuit (3D-IC) technology, often referred to as through-silicon via (TSV) formation technology, has been steadily maturing and is increasingly used in advanced semic... » read more

Open-Source And Royalty-Free Confidential Computing For Embedded RISC-V Systems (IBM, Max Planck)
By Technical Paper Link - 20 May, 2025 - Comments: 0

A new technical paper titled "ACE: Confidential Computing for Embedded RISC-V Systems" was published by researchers at IBM Research, IBM T.J. Watson Research Center, Max Planck Institute for Software Systems (MPI-SWS). Abstract "Confidential computing plays an important role in isolating sensitive applications from the vast amount of untrusted code commonly found in the modern cloud. We a... » read more

Energy-Aware DL: The Interplay Between NN Efficiency And Hardware Constraints (Imperial College London, Cambridge)
By Technical Paper Link - 20 May, 2025 - Comments: 0

A new technical paper titled "Energy-Aware Deep Learning on Resource-Constrained Hardware" was published by researchers at Imperial College London and University of Cambridge. Abstract "The use of deep learning (DL) on Internet of Things (IoT) and mobile devices offers numerous advantages over cloud-based processing. However, such devices face substantial energy constraints to prolong batte... » read more

Cache Side-Channel Attacks On LLMs (MITRE, WPI)
By Technical Paper Link - 18 May, 2025 - Comments: 0

A new technical paper titled "Spill The Beans: Exploiting CPU Cache Side-Channels to Leak Tokens from Large Language Models" was published by researchers at MITRE and Worcester Polytechnic Institute. Abstract "Side-channel attacks on shared hardware resources increasingly threaten confidentiality, especially with the rise of Large Language Models (LLMs). In this work, we introduce Spill The... » read more

Effects Of Hardware Prefetchers For Scientific Application Kernels Running on High-End Processors
By Technical Paper Link - 14 May, 2025 - Comments: 0

A new technical paper titled "Memory Prefetching Evaluation of Scientific Applications on A Modern HPC Arm-based Processor" was published by researchers at Jülich Supercomputing Centre and KTH Royal Institute of Technology. Abstract "Memory prefetching is a well-known technique for mitigating the negative impact of memory access latencies on memory bandwidth. This problem has become more p... » read more

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