category: Memory

category: IoT, Security & Automotive

Neuromorphic Computing: Self-Adapting HW With ReRAMs
By Technical Paper Link - 03 Apr, 2023 - Comments: 0

A new technical paper titled "A self-adaptive hardware with resistive switching synapses for experience-based neurocomputing" was published by researchers at Infineon Technologies, Politecnico di Milano and IUNET, Weebit Nano, and CEA Leti. Abstract "Neurobiological systems continually interact with the surrounding environment to refine their behaviour toward the best possible reward. Achie... » read more

CXL Memory: Detailed Characterization Analysis Using Micro-Benchmarks And Real Applications (UIUC, Intel Labs)
By Technical Paper Link - 30 Mar, 2023 - Comments: 0

A new technical paper titled "Demystifying CXL Memory with Genuine CXL-Ready Systems and Devices" was published by researchers at University of Illinois Urbana-Champaign (UIUC) and Intel Labs. Abstract: "The high demand for memory capacity in modern datacenters has led to multiple lines of innovation in memory expansion and disaggregation. One such effort is Compute eXpress Link (CXL)-based... » read more

Interconnects: Exploring Semi-Metals (Penn State, IBM, Rice University)
By Technical Paper Link - 26 Mar, 2023 - Comments: 0

A technical paper titled "Exploring Topological Semi-Metals for Interconnects" was published by researchers at Penn State, IBM, and Rice University, with funding by Semiconductor Research Corporation (SRC). Abstract "The size of transistors has drastically reduced over the years. Interconnects have likewise also been scaled down. Today, conventional copper (Cu)-based interconnects face a ... » read more

Feasibility of Using Domain Wall-Magnetic Tunnel Junction for Magnetic Analog Addressable Memories
By Technical Paper Link - 23 Mar, 2023 - Comments: 0

A new technical paper titled "Domain Wall-Magnetic Tunnel Junction Analog Content Addressable Memory Using Current and Projected Data" was published by researchers at UT Austin and Samsung Advanced Institute of Technology (SAIT). Abstract "With the rise in in-memory computing architectures to reduce the compute-memory bottleneck, a new bottleneck is present between analog and digital conver... » read more

New Spintronics Manufacturing Process, Allowing Scaling Down To Sub-5nm (U. of Minnesota/NIST)
By Technical Paper Link - 20 Mar, 2023 - Comments: 0

A new technical paper titled "Sputtered L10-FePd and its Synthetic Antiferromagnet on Si/SiO2 Wafers for Scalable Spintronics" was published by researchers at University of Minnesota and NIST, with funding by DARPA and others. According to a University of Minnesota summary news article, "The industry standard spintronic material, cobalt iron boron, has reached a limit in its scalability. The... » read more

Solving The Reliability Problem Of Memristor-Based Artificial Neural Networks
By Technical Paper Link - 19 Mar, 2023 - Comments: 0

A technical paper titled "ReMeCo: Reliable Memristor-Based in-Memory Neuromorphic Computation" was published by researchers at Eindhoven University of Technology, University of Tehran, and USC. Abstract: "Memristor-based in-memory neuromorphic computing systems promise a highly efficient implementation of vector-matrix multiplications, commonly used in artificial neural networks (ANNs). H... » read more

Shift Register-In-Memory Architecture
By Technical Paper Link - 19 Mar, 2023 - Comments: 0

A new technical paper titled "Toward Single-Cell Multiple-Strategy Processing Shift Register Powered by Phase-Change Memory Materials" was published by researchers at Singapore University of Technology and Design and University of Cambridge. Abstract "Modern innovations are built on the foundation of computers. Compared to von Neumann architectures having separate storage and processing uni... » read more

Reducing The Cost of Cache Coherence By Integrating HW Coherence Protocol Directly With The Programming Language
By Technical Paper Link - 19 Mar, 2023 - Comments: 0

A new technical paper titled "WARDen: Specializing Cache Coherence for High-Level Parallel Languages" was published by researchers at Northwestern University and Carnegie Mellon University. Abstract: "High-level parallel languages (HLPLs) make it easier to write correct parallel programs. Disciplined memory usage in these languages enables new optimizations for hardware bottlenecks, such ... » read more

FPGA-based Infrastructure, With RISC-V Prototype, to Enable Implementation & Evaluation of Cross-Layer Techniques in Real HW (Best Paper Award)
By Technical Paper Link - 15 Mar, 2023 - Comments: 0

A technical paper titled "MetaSys: A Practical Open-Source Metadata Management System to Implement and Evaluate Cross-Layer Optimizations" was published by researchers at University of Toronto, ETH Zurich, and Carnegie Mellon University. This paper won the Best Paper Award at the HiPEAC 2023 conference. Abstract: "This paper introduces the first open-source FPGA-based infrastructure, MetaSy... » read more

Co-Design View of Cross-Bar Based Compute-In-Memory
By Technical Paper Link - 15 Mar, 2023 - Comments: 0

A new review paper titled "Compute in-Memory with Non-Volatile Elements for Neural Networks: A Review from a Co-Design Perspective" was published by researchers at Argonne National Lab, Purdue University, and Indian Institute of Technology Madras. "With an over-arching co-design viewpoint, this review assesses the use of cross-bar based CIM for neural networks, connecting the material proper... » read more

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