category: Memory

category: IoT, Security & Automotive

Gem5 Simulation Environment With Customized RISC-V Instructions for LIM Architectures
By Technical Paper Link - 09 Apr, 2023 - Comments: 0

A new technical paper titled "Simulation Environment with Customized RISC-V Instructions for Logic-in-Memory Architectures" was published by researchers at National Tsing-Hua University, Politecnico di Torino, University of Rome Tor Vergata, and University of Twente. Abstract "Nowadays, various memory-hungry applications like machine learning algorithms are knocking "the memory wall". Tow... » read more

Low-Power Heterogeneous Compute Cluster For TinyML DNN Inference And On-Chip Training
By Technical Paper Link - 09 Apr, 2023 - Comments: 0

A new technical paper titled "DARKSIDE: A Heterogeneous RISC-V Compute Cluster for Extreme-Edge On-Chip DNN Inference and Training" was published by researchers at University of Bologna and ETH Zurich. Abstract "On-chip deep neural network (DNN) inference and training at the Extreme-Edge (TinyML) impose strict latency, throughput, accuracy, and flexibility requirements. Heterogeneous clus... » read more

Google’s TPU v4 Architecture: 3 Major Features
By Technical Paper Link - 07 Apr, 2023 - Comments: 0

A new technical paper titled "TPU v4: An Optically Reconfigurable Supercomputer for Machine Learning with Hardware Support for Embeddings" was published by researchers at Google. Abstract: "In response to innovations in machine learning (ML) models, production workloads changed radically and rapidly. TPU v4 is the fifth Google domain specific architecture (DSA) and its third supercomputer f... » read more

Neuromorphic Computing: Self-Adapting HW With ReRAMs
By Technical Paper Link - 03 Apr, 2023 - Comments: 0

A new technical paper titled "A self-adaptive hardware with resistive switching synapses for experience-based neurocomputing" was published by researchers at Infineon Technologies, Politecnico di Milano and IUNET, Weebit Nano, and CEA Leti. Abstract "Neurobiological systems continually interact with the surrounding environment to refine their behaviour toward the best possible reward. Achie... » read more

CXL Memory: Detailed Characterization Analysis Using Micro-Benchmarks And Real Applications (UIUC, Intel Labs)
By Technical Paper Link - 30 Mar, 2023 - Comments: 0

A new technical paper titled "Demystifying CXL Memory with Genuine CXL-Ready Systems and Devices" was published by researchers at University of Illinois Urbana-Champaign (UIUC) and Intel Labs. Abstract: "The high demand for memory capacity in modern datacenters has led to multiple lines of innovation in memory expansion and disaggregation. One such effort is Compute eXpress Link (CXL)-based... » read more

Interconnects: Exploring Semi-Metals (Penn State, IBM, Rice University)
By Technical Paper Link - 26 Mar, 2023 - Comments: 0

A technical paper titled "Exploring Topological Semi-Metals for Interconnects" was published by researchers at Penn State, IBM, and Rice University, with funding by Semiconductor Research Corporation (SRC). Abstract "The size of transistors has drastically reduced over the years. Interconnects have likewise also been scaled down. Today, conventional copper (Cu)-based interconnects face a ... » read more

Feasibility of Using Domain Wall-Magnetic Tunnel Junction for Magnetic Analog Addressable Memories
By Technical Paper Link - 23 Mar, 2023 - Comments: 0

A new technical paper titled "Domain Wall-Magnetic Tunnel Junction Analog Content Addressable Memory Using Current and Projected Data" was published by researchers at UT Austin and Samsung Advanced Institute of Technology (SAIT). Abstract "With the rise in in-memory computing architectures to reduce the compute-memory bottleneck, a new bottleneck is present between analog and digital conver... » read more

New Spintronics Manufacturing Process, Allowing Scaling Down To Sub-5nm (U. of Minnesota/NIST)
By Technical Paper Link - 20 Mar, 2023 - Comments: 0

A new technical paper titled "Sputtered L10-FePd and its Synthetic Antiferromagnet on Si/SiO2 Wafers for Scalable Spintronics" was published by researchers at University of Minnesota and NIST, with funding by DARPA and others. According to a University of Minnesota summary news article, "The industry standard spintronic material, cobalt iron boron, has reached a limit in its scalability. The... » read more

Solving The Reliability Problem Of Memristor-Based Artificial Neural Networks
By Technical Paper Link - 19 Mar, 2023 - Comments: 0

A technical paper titled "ReMeCo: Reliable Memristor-Based in-Memory Neuromorphic Computation" was published by researchers at Eindhoven University of Technology, University of Tehran, and USC. Abstract: "Memristor-based in-memory neuromorphic computing systems promise a highly efficient implementation of vector-matrix multiplications, commonly used in artificial neural networks (ANNs). H... » read more

Shift Register-In-Memory Architecture
By Technical Paper Link - 19 Mar, 2023 - Comments: 0

A new technical paper titled "Toward Single-Cell Multiple-Strategy Processing Shift Register Powered by Phase-Change Memory Materials" was published by researchers at Singapore University of Technology and Design and University of Cambridge. Abstract "Modern innovations are built on the foundation of computers. Compared to von Neumann architectures having separate storage and processing uni... » read more

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