category: Memory

category: IoT, Security & Automotive

RISC-V decoupled Vector Processing Unit (VPU) For HPC
By Technical Paper Link - 20 Dec, 2022 - Comments: 0

A technical paper titled "Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications" was published by researchers at Barcelona Supercomputing Center, Spain. "The maturity level of RISC-V and the availability of domain-specific instruction set extensions, like vector processing, make RISC-V a good candidate for supporting the integration of ... » read more

Safeguarding SRAMs From IP Theft (Best Paper Award)
By Technical Paper Link - 15 Dec, 2022 - Comments: 0

A technical paper titled "Beware of Discarding Used SRAMs: Information is Stored Permanently" was published by researchers at Auburn University. The paper won "Best Paper Award" at the IEEE International Conference on Physical Assurance and Inspection of Electronics (PAINE) Oct. 25-27 in Huntsville. Abstract: "Data recovery has long been a focus of the electronics industry for decades by s... » read more

Step Towards A 5G Software-Defined RAN Over A Fully Open-Source Parallel RISC-V Architecture (ETH Zurich)
By Technical Paper Link - 15 Dec, 2022 - Comments: 0

A technical paper titled "Efficient Parallelization of 5G-PUSCH on a Scalable RISC-V Many-core Processor" was published by researchers at ETH Zurich. Abstract (partial) "5G Radio access network disaggregation and softwarization pose challenges in terms of computational performance to the processing units. At the physical layer level, the baseband processing computational effort is typicall... » read more

Heterogeneous Ultra-Low-Power RISC-V SoC Running Linux
By Technical Paper Link - 13 Dec, 2022 - Comments: 0

A technical paper titled "HULK-V: a Heterogeneous Ultra-low-power Linux capable RISC-V SoC" was published by researchers at University of Bologna, University of Modena and Reggio Emilia, and ETH Zurich. "We present HULK-V: an open-source Heterogeneous Linux-capable RISC-V-based SoC coupling a 64-bit RISC-V processor with an 8-core Programmable Multi-Core Accelerator (PMCA), delivering up to... » read more

Leveraging Multi-Agent RL for Microprocessor Design Space (Harvard, Google)
By Technical Paper Link - 13 Dec, 2022 - Comments: 0

A new technical paper titled "Multi-Agent Reinforcement Learning for Microprocessor Design Space Exploration" was published by researchers at Harvard University and Google research groups. Abstract "Microprocessor architects are increasingly resorting to domain-specific customization in the quest for high-performance and energy-efficiency. As the systems grow in complexity, fine-tuning arch... » read more

2D-Materials-Based Electronic Circuits (KAUST and TSMC)
By Technical Paper Link - 06 Dec, 2022 - Comments: 0

A special edition article titled "Electronic Circuits made of 2D Materials" was just published by Dr. Mario Lanza, KAUST Associate Professor of Material Science and Engineering, and Iuliana Radu, corporate researcher at TSMC. This special issue covers 21 articles from leading subject matter experts, ranging from materials synthesis and their integration in micro/nano-electronic devices and c... » read more

Fabricating FeFET Devices with Silicon-Doped Hafnium Oxide As A Ferroelectric Layer
By Technical Paper Link - 06 Dec, 2022 - Comments: 0

A new technical paper titled "Synergistic Approach of Interfacial Layer Engineering and READ-Voltage Optimization in HfO2-Based FeFETs for In-Memory-Computing Applications" was published by researchers at Fraunhofer IPMS, GlobalFoundries, and TU Bergakademie Freiberg. Abstract (partial) "This article reports an improvement in the performance of the hafnium oxide-based (HfO2) ferroelectric... » read more

Hardware Trojans Target Coherence Systems in Chiplets (Texas A&M / NYU)
By Technical Paper Link - 01 Dec, 2022 - Comments: 0

A technical paper titled "Hardware Trojan Threats to Cache Coherence in Modern 2.5D Chiplet Systems" was published by researchers at Texas A&M University and NYU. Abstract: "As industry moves toward chiplet-based designs, the insertion of hardware Trojans poses a significant threat to the security of these systems. These systems rely heavily on cache coherence for coherent data communic... » read more

HW Accelerator Architecture for MI Computation With Low Latency, Energy Efficient (MIT)
By Technical Paper Link - 01 Dec, 2022 - Comments: 0

A new technical paper titled "Efficient Computation of Map-scale Continuous Mutual Information on Chip in Real Time" was published by researchers at MIT. Find the technical paper here. "In this paper, we introduce a new hardware accelerator architecture for MI computation that features a low-latency, energy-efficient MI compute core and an optimized memory subsystem that provides sufficie... » read more

MAC Operation on 28nm High-k Metal Gate FeFET-based Memory Array with ADC (Fraunhofer IPMS/GF)
By Technical Paper Link - 01 Dec, 2022 - Comments: 0

A technical paper titled "Demonstration of Multiply-Accumulate Operation With 28 nm FeFET Crossbar Array" was published by researchers at Fraunhofer IPMS and GlobalFoundries. Abstract "This letter reports a linear multiply-accumulate (MAC) operation conducted on a crossbar memory array based on 28nm high-k metal gate (HKMG) Complementary Metal Oxide Semiconductor (CMOS) and ferroelectric fi... » read more

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