category: Memory

category: IoT, Security & Automotive

Structural Phase Transition In Minute Detail On A Very Fast Timescale–A Path To Improved Computer Memories (Argonne National Lab)
By Technical Paper Link - 07 Sep, 2022 - Comments: 0

A new technical paper titled "X-ray nanodiffraction imaging reveals distinct nanoscopic dynamics of an ultrafast phase transition" was published by researchers at Argonne National Lab, UCSD, and the University of Wisconsin–Madison. According to Argonne National Lab's news release," researchers have for the first time been able to look at a structural phase transition in minute detail on a ... » read more

3D NAND: Scenarios For Scaling & Stacking
By Technical Paper Link - 25 Aug, 2022 - Comments: 0

A new research paper titled "Impact of Stacking-Up and Scaling-Down Bit Cells in 3D NAND on Their Threshold Voltages" was published by researchers at Sungkyunkwan University and Korea University. Abstract "Over the past few decades, NAND flash memory has advanced with exponentially-increasing bit growth. As bit cells in 3D NAND flash memory are stacked up and scaled down together, some pote... » read more

Finding the Scope of CXL-Enabled Tiered Memory System in Production
By Technical Paper Link - 25 Aug, 2022 - Comments: 0

This new technical paper titled "TPP: Transparent Page Placement for CXL-Enabled Tiered Memory" is presented by researchers at University of Michigan and Meta Inc. Abstract (partial) "We propose a novel OS-level application-transparent page placement mechanism (TPP) for efficient memory management. TPP employs a lightweight mechanism to identify and place hot and cold pages to appropriate... » read more

Polynesia, A Novel Hardware/Software Cooperative Design for In-Memory HTAP Databases
By Technical Paper Link - 22 Aug, 2022 - Comments: 0

A team of researchers from ETH Zurich, Google and Univ. of Illinois Urbana-Champaign recently published a technical paper titled "Polynesia: Enabling High-Performance and Energy-Efficient Hybrid Transactional/Analytical Databases with Hardware/Software Co-Design". Abstract (partial) "We propose Polynesia, a hardware–software co-designed system for in-memory HTAP [hybrid transactional/anal... » read more

Efficient Neuromorphic AI Chip: “NeuroRRAM”
By Technical Paper Link - 17 Aug, 2022 - Comments: 0

New technical paper titled "A compute-in-memory chip based on resistive random-access memory" was published by a team of international researchers at Stanford, UCSD, University of Pittsburgh, University of Notre Dame and Tsinghua University. The paper's abstract states "by co-optimizing across all hierarchies of the design from algorithms and architecture to circuits and devices, we present ... » read more

An Escalation of Rowhammer To Rows Beyond Immediate Neighbors
By Technical Paper Link - 15 Aug, 2022 - Comments: 0

Researchers at Graz University of Technology, Lamarr Security Research, Google, AWS, and Rivos presented this new technical paper titled "Half-Double: Hammering From the Next Row Over" at the USENIX Security Symposium in Boston in August 2022. Abstract: "Rowhammer is a vulnerability in modern DRAM where repeated accesses to one row (the aggressor) give off electrical disturbance whose cumu... » read more

Fully CMOS-compatible Ternary Inverter with a Memory Function Using Silicon Feedback Field-Effect Transistors (FBFETs)
By Technical Paper Link - 02 Aug, 2022 - Comments: 0

New technical paper titled "New ternary inverter with memory function using silicon feedback field-effect transistors" was published from researchers at Korea University. Abstract: In this study, we present a fully complementary metal–oxide–semiconductor-compatible ternary inverter with a memory function using silicon feedback field-effect transistors (FBFETs). FBFETs operate with a pos... » read more

Edge-AI Hardware for Extended Reality
By Technical Paper Link - 20 Jul, 2022 - Comments: 0

New technical paper titled "Memory-Oriented Design-Space Exploration of Edge-AI Hardware for XR Applications" from researchers at Indian Institute of Technology Delhi and Reality Labs Research, Meta. Abstract "Low-Power Edge-AI capabilities are essential for on-device extended reality (XR) applications to support the vision of Metaverse. In this work, we investigate two representative XR w... » read more

Reduce RowHammer Vulnerability By Reducing Wordline Voltage
By Technical Paper Link - 18 Jul, 2022 - Comments: 0

Researchers from ETH Zurich present a new technical paper titled "Understanding RowHammer Under Reduced Wordline Voltage: An Experimental Study Using Real DRAM Devices." Abstract (Partial) "This is the first work to experimentally demonstrate on 272 real DRAM chips that lowering VPP reduces a DRAM chip's RowHammer vulnerability. We show that lowering VPP 1) increases the number of activat... » read more

DRAM Chips That Employ On-Die Error Correction & Related Reliability Techniques
By Technical Paper Link - 16 Jul, 2022 - Comments: 0

This new PhD thesis paper titled "Enabling Effective Error Mitigation in Memory Chips That Use On-Die Error-Correcting Codes" from ETH Zurich researcher Minesh Patel won the IEEE  William C. Carter Award in June 2022. Abstract "Improvements in main memory storage density are primarily driven by process technology scaling, which negatively impacts reliability by exacerbating various circu... » read more

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