ETH Zurich Introduces ProTRR, in-DRAM Rowhammer Mitigation


New technical paper titled "PROTRR: Principled yet Optimal In-DRAM Target Row Refresh" from ETH Zurich. The paper was presented at the 43rd IEEE Symposium on Security and Privacy (SP 2022), San Francisco, CA, USA, May 22–26, 2022. This new paper introduces ProTRR, an "in-DRAM Rowhammer mitigation that is secure against FEINTING, a novel Rowhammer attack." The related video presentation can... » read more

Neuromorphic HW Fabric That Supports A Recently Proposed Class of Stochastic Neural Network


New research paper titled "Neural sampling machine with stochastic synapse allows brain-like learning and inference" from University of Notre Dame and Department of Cognitive Sciences, University of California Irvine. Abstract "Many real-world mission-critical applications require continual online learning from noisy data and real-time decision making with a defined confidence level. Brain-... » read more

Using Dynamic Route Map Technique for Insight Into Memristors


New technical paper titled "Empirical Characterization of ReRAM Devices Using Memory Maps and a Dynamic Route Map," from Balearic Islands University, UC Berkeley, Health Institute of the Balearic Islands, International Hellenic University, Technische Universität Dresden, Universidad de Valladolid, and Aristotle University of Thessaloniki. Abstract: "Memristors were proposed in the early 1... » read more

Computational SRAM (C-SRAM) Solution Combining In- and Near-Memory Computing Approaches


New academic paper titled "Towards a Truly Integrated Vector Processing Unit for Memory-bound Applications Based on a Cost-competitive Computational SRAM Design Solution", from researchers at Univ. Grenoble Alpes, CEA-LIST. Abstract "This article presents Computational SRAM (C-SRAM) solution combining In- and Near-Memory Computing approaches. It allows performing arithmetic, logic, and co... » read more

Neurosynaptic Device That Mimics Synaptic and Intrinsic Plasticity Concomitantly In a Single cell


New academic paper titled "Simultaneous emulation of synaptic and intrinsic plasticity using a memristive synapse" from researchers at Korea Advanced Institute of Science and Technology (KAIST). Abstract Neuromorphic computing targets the hardware embodiment of neural network, and device implementation of individual neuron and synapse has attracted considerable attention. The emulation of... » read more

SOT-MRAM-based CIM architecture for a CNN model


New research paper "In-Memory Computing Architecture for a Convolutional Neural Network Based on Spin Orbit Torque MRAM", from National Taiwan University, Feng Chia University, Chung Yuan Christian University. Abstract "Recently, numerous studies have investigated computing in-memory (CIM) architectures for neural networks to overcome memory bottlenecks. Because of its low delay, high energ... » read more

Vertically stacked, low-voltage organic ternary logic circuits including nonvolatile floating-gate memory transistors


Research paper from KAIST and Gachon University. Abstract "Multi-valued logic (MVL) circuits based on heterojunction transistor (HTR) have emerged as an effective strategy for high-density information processing without increasing the circuit complexity. Herein, an organic ternary logic inverter (T-inverter) is demonstrated, where a nonvolatile floating-gate flash memory is employed to ... » read more

Analog Edge Inference with ReRAM


Abstract "As the demands of big data applications and deep learning continue to rise, the industry is increasingly looking to artificial intelligence (AI) accelerators. Analog in-memory computing (AiMC) with emerging nonvolatile devices enable good hardware solutions, due to its high energy efficiency in accelerating the multiply-and-accumulation (MAC) operation. Herein, an Applied Materials... » read more

A Case for Transparent Reliability in DRAM Systems


New technical paper from ETH Zurich and TU Delft. Abstract "Today's systems have diverse needs that are difficult to address using one-size-fits-all commodity DRAM. Unfortunately, although system designers can theoretically adapt commodity DRAM chips to meet their particular design goals (e.g., by reducing access timings to improve performance, implementing system-level RowHammer mitigati... » read more

Memory Bandwidth Regulation on Hybrid NVM/DRAM Platforms


New technical paper from Shanghai Jiao Tong University Abstract "Non-volatile memory (NVM) has emerged as a new memory media, resulting in a hybrid NVM/DRAM configuration in typical servers. Memory-intensive applications competing for the scant memory bandwidth can yield degraded performance. Identifying the noisy neighbors and regulating the memory bandwidth usage of them can alleviate th... » read more

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