category: Memory

category: IoT, Security & Automotive

Framework Based on an RISC-V Microprocessor Supporting LiM Operations
By Technical Paper Link - 29 Sep, 2022 - Comments: 0

A new technical paper titled "RISC-Vlim, a RISC-V Framework for Logic-in-Memory Architectures" was published by researchers at Politecnico di Torino (Italy), Univerity of Tor Vergata (Italy), and University of Twente (The Netherlands). Abstract: "Most modern CPU architectures are based on the von Neumann principle, where memory and processing units are separate entities. Although processin... » read more

Decreasing Refresh Latency of Off-the-Shelf DRAM Chips
By Technical Paper Link - 28 Sep, 2022 - Comments: 0

A new technical paper titled "HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips" was published by researchers at ETH Zürich, TOBB University of Economics and Technology and Galicia Supercomputing Center (CESGA). Abstract "DRAM is the building block of modern main memory systems. DRAM cells must be periodically refreshed to prevent data loss. Refresh oper... » read more

Setting The Memory Controller Free From Managing DRAM Maintenance Ops (ETH Zurich)
By Technical Paper Link - 14 Sep, 2022 - Comments: 0

A new technical paper titled "A Case for Self-Managing DRAM Chips: Improving Performance, Efficiency, Reliability, and Security via Autonomous in-DRAM Maintenance Operations" was published by researchers at ETH Zurich. Abstract: "The rigid interface of current DRAM chips places the memory controller completely in charge of DRAM control. Even DRAM maintenance operations, which are used to en... » read more

Radiation-Hardened Non-Volatile Magnetic Latch That Tolerates SNUs and DNUs
By Technical Paper Link - 13 Sep, 2022 - Comments: 0

A research paper titled "A Radiation-Hardened Non-Volatile Magnetic Latch with High Reliability and Persistent Storage" was published by researchers at Anhui University, Hefei University of Technology, LIRMM, and Kyutech. According to the abstract: "Based on an advanced triple-path dual-interlocked-storage-cell (TPDICE) and MTJs, this paper proposes a radiation-hardened non-volatile magneti... » read more

Structural Phase Transition In Minute Detail On A Very Fast Timescale–A Path To Improved Computer Memories (Argonne National Lab)
By Technical Paper Link - 07 Sep, 2022 - Comments: 0

A new technical paper titled "X-ray nanodiffraction imaging reveals distinct nanoscopic dynamics of an ultrafast phase transition" was published by researchers at Argonne National Lab, UCSD, and the University of Wisconsin–Madison. According to Argonne National Lab's news release," researchers have for the first time been able to look at a structural phase transition in minute detail on a ... » read more

3D NAND: Scenarios For Scaling & Stacking
By Technical Paper Link - 25 Aug, 2022 - Comments: 0

A new research paper titled "Impact of Stacking-Up and Scaling-Down Bit Cells in 3D NAND on Their Threshold Voltages" was published by researchers at Sungkyunkwan University and Korea University. Abstract "Over the past few decades, NAND flash memory has advanced with exponentially-increasing bit growth. As bit cells in 3D NAND flash memory are stacked up and scaled down together, some pote... » read more

Finding the Scope of CXL-Enabled Tiered Memory System in Production
By Technical Paper Link - 25 Aug, 2022 - Comments: 0

This new technical paper titled "TPP: Transparent Page Placement for CXL-Enabled Tiered Memory" is presented by researchers at University of Michigan and Meta Inc. Abstract (partial) "We propose a novel OS-level application-transparent page placement mechanism (TPP) for efficient memory management. TPP employs a lightweight mechanism to identify and place hot and cold pages to appropriate... » read more

Polynesia, A Novel Hardware/Software Cooperative Design for In-Memory HTAP Databases
By Technical Paper Link - 22 Aug, 2022 - Comments: 0

A team of researchers from ETH Zurich, Google and Univ. of Illinois Urbana-Champaign recently published a technical paper titled "Polynesia: Enabling High-Performance and Energy-Efficient Hybrid Transactional/Analytical Databases with Hardware/Software Co-Design". Abstract (partial) "We propose Polynesia, a hardware–software co-designed system for in-memory HTAP [hybrid transactional/anal... » read more

Efficient Neuromorphic AI Chip: “NeuroRRAM”
By Technical Paper Link - 17 Aug, 2022 - Comments: 0

New technical paper titled "A compute-in-memory chip based on resistive random-access memory" was published by a team of international researchers at Stanford, UCSD, University of Pittsburgh, University of Notre Dame and Tsinghua University. The paper's abstract states "by co-optimizing across all hierarchies of the design from algorithms and architecture to circuits and devices, we present ... » read more

An Escalation of Rowhammer To Rows Beyond Immediate Neighbors
By Technical Paper Link - 15 Aug, 2022 - Comments: 0

Researchers at Graz University of Technology, Lamarr Security Research, Google, AWS, and Rivos presented this new technical paper titled "Half-Double: Hammering From the Next Row Over" at the USENIX Security Symposium in Boston in August 2022. Abstract: "Rowhammer is a vulnerability in modern DRAM where repeated accesses to one row (the aggressor) give off electrical disturbance whose cumu... » read more

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