category: Memory

category: IoT, Security & Automotive

Training Large LLM Models With Billions To Trillion Parameters On ORNL’s Frontier Supercomputer
By Technical Paper Link - 16 Jan, 2024 - Comments: 0

A technical paper titled “Optimizing Distributed Training on Frontier for Large Language Models” was published by researchers at Oak Ridge National Laboratory (ORNL) and Universite Paris-Saclay. Abstract: "Large language models (LLMs) have demonstrated remarkable success as foundational models, benefiting various downstream applications through fine-tuning. Recent studies on loss scaling ... » read more

Novel Neuromorphic Artificial Neural Network Circuit Architecture
By Technical Paper Link - 15 Jan, 2024 - Comments: 0

A technical paper titled “Mosaic: in-memory computing and routing for small-world spike-based neuromorphic systems” was published by researchers at CEA-LETI Université Grenoble Alpes, University of Zurich and ETH Zurich. Abstract: "The brain’s connectivity is locally dense and globally sparse, forming a small-world graph—a principle prevalent in the evolution of various species, sugg... » read more

Suitability of FeFET-Based CAM Cells For Storage-Class Memory, Under Junction Temperature Variations
By Technical Paper Link - 15 Jan, 2024 - Comments: 0

A technical paper titled “Ferroelectric Field Effect Transistors–Based Content-Addressable Storage-Class Memory: A Study on the Impact of Device Variation and High-Temperature Compatibility” was published by researchers at Fraunhofer Institute for Photonic Microsystems (IPMS) and Indian Institute of Technology Madras (IIT Madras). Abstract: "Hafnium oxide (HfO2)-based ferroelectric fiel... » read more

Ferroelectric Tunnel Junctions In Crossbar Array Analog In-Memory Compute Accelerators
By Technical Paper Link - 11 Jan, 2024 - Comments: 0

A technical paper titled “Ferroelectric Tunnel Junction Memristors for In-Memory Computing Accelerators” was published by researchers at Lund University. Abstract: "Neuromorphic computing has seen great interest as leaps in artificial intelligence (AI) applications have exposed limitations due to heavy memory access, with the von Neumann computing architecture. The parallel in-memory comp... » read more

Demonstrating A 2D–0D Hybrid Optical Multi-Level Memory Device Operated By Laser Pulses
By Technical Paper Link - 11 Jan, 2024 - Comments: 0

A technical paper titled “Probing Optical Multi-Level Memory Effects in Single Core–Shell Quantum Dots and Application Through 2D-0D Hybrid Inverters” was published by researchers at Korea Institute of Science and Technology (KIST), Korea University, Daegu Gyeongbuk Institute of Science and Technology (DGIST), National Institute for Materials Science (Japan), and University of Science and... » read more

Efficient LLM Inference With Limited Memory (Apple)
By Technical Paper Link - 04 Jan, 2024 - Comments: 0

A technical paper titled “LLM in a flash: Efficient Large Language Model Inference with Limited Memory” was published by researchers at Apple. Abstract: "Large language models (LLMs) are central to modern natural language processing, delivering exceptional performance in various tasks. However, their intensive computational and memory requirements present challenges, especially for device... » read more

Large-Scale Integration Of 2D Materials As The Semiconducting Channel In An In-Memory Processor (EPFL)
By Technical Paper Link - 03 Jan, 2024 - Comments: 0

A technical paper titled “A large-scale integrated vector-matrix multiplication processor based on monolayer molybdenum disulfide memories” was published by researchers at École Polytechnique Fédérale de Lausanne (EPFL). Abstract: "Data-driven algorithms—such as signal processing and artificial neural networks—are required to process and extract meaningful information from the mass... » read more

Mixed SRAM And eDRAM Cell For Area And Energy-Efficient On-Chip AI Memory (Yale Univ.)
By Technical Paper Link - 21 Dec, 2023 - Comments: 0

A new technical paper titled "MCAIMem: a Mixed SRAM and eDRAM Cell for Area and Energy-efficient on-chip AI Memory" was published by researchers at Yale University. Abstract: "AI chips commonly employ SRAM memory as buffers for their reliability and speed, which contribute to high performance. However, SRAM is expensive and demands significant area and energy consumption. Previous studies... » read more

Analog Planar Memristor Device: Developing, Designing, and Manufacturing
By Technical Paper Link - 20 Dec, 2023 - Comments: 0

A new technical paper titled "Analog monolayer SWCNTs-based memristive 2D structure for energy-efficient deep learning in spiking neural networks" was published by researchers at Delft University of Technology and Khalifa University. Abstract: "Advances in materials science and memory devices work in tandem for the evolution of Artificial Intelligence systems. Energy-efficient computation... » read more

Memory Devices-Based Bayesian Neural Networks For Edge AI
By Technical Paper Link - 20 Dec, 2023 - Comments: 0

A new technical paper titled "Bringing uncertainty quantification to the extreme-edge with memristor-based Bayesian neural networks" was published by researchers at Université Grenoble Alpes, CEA, LETI, and CNRS. Abstract: "Safety-critical sensory applications, like medical diagnosis, demand accurate decisions from limited, noisy data. Bayesian neural networks excel at such tasks, offering... » read more

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