SiC Power Electronics Packaging: Floating Die Structure and Liquid Metal Fluidic Connection (Cambridge U. )


A new technical paper titled "Liquid Metal Fluidic Connection and Floating Die Structure for Ultralow Thermomechanical Stress of SiC Power Electronics Packaging" was published by researchers at Cambridge University. Abstract "Coefficients of thermal expansion (CTE) of various materials in packaging structure layers vary largely, causing significant thermomechanical stress in power electroni... » read more

Step Towards 3D PICs: Low Loss Fiber-Coupled Interconnects (UIUC)


A new technical paper titled "Low loss fiber-coupled volumetric interconnects fabricated via direct laser writing" was published by researchers at University of Illinois Urbana-Champaign (UIUC). Abstract "Photonic integrated circuits (PICs) are vital for high-speed data transmission. However, optical routing is limited in PICs composed of only one or a few stacked planes. Further, coupling ... » read more

Overview of Test Strategies for 3DICs


A new technical paper titled "Design-for-Test Solutions for 3D Integrated Circuits" was published by researchers at Duke University, Arizona State University, and NVIDIA. Abstract: "As Moore's Law approaches its limits, 3D integrated circuits (ICs) have emerged as promising alternatives to conventional scaling methodologies. However, the benefits of 3D integration in terms of lower power co... » read more

Power Electronic Packaging for Discrete Dies


A technical paper titled “Substrate Embedded Power Electronics Packaging for Silicon Carbide MOSFETs” was published by researchers at University of Cambridge, University of Warwick, Chongqing University, and SpaceX. Abstract: "This paper proposes a new power electronic packaging for discrete dies, namely Standard Cell which consists of a step-etched active metal brazed (AMB) substrate and... » read more

Probing Attacks Against Chiplets


A technical paper titled “Evaluating Vulnerability of Chiplet-Based Systems to Contactless Probing Techniques” was published by researchers at University of Massachusetts and Worcester Polytechnic Institute. Abstract: "Driven by a need for ever increasing chip performance and inclusion of innovative features, a growing number of semiconductor companies are opting for all-inclusive System-... » read more

Adoption of Chiplet Technology in the Automotive Industry


A technical paper titled "Chiplets on Wheels: Review Paper on Holistic Chiplet Solutions for Autonomous Vehicles" was published by researchers at the Indian Institute of Technology, Madras. Abstract "On the advent of the slow death of Moore's law, the silicon industry is moving towards a new era of chiplets. The automotive industry is experiencing a profound transformation towards software-... » read more

Comparing Thermal Properties In Molybdenum Substrate To Si And Glass For A System-On-Foil Integration (RIT, Lux)


A technical paper titled “Comparative Analysis of Thermal Properties in Molybdenum Substrate to Silicon and Glass for a System-on-Foil Integration” was published by researchers at Rochester Institute of Technology and Lux Semiconductors. Abstract: "Advanced electronics technology is moving towards smaller footprints and higher computational power. In order to achieve this, advanced packag... » read more

Physics-Based Digital Twin of a Thermally Aged Flip-Chip Package (TU Delft, NXP)


A technical paper titled “Modelling thermomechanical degradation of moulded electronic packages using physics-based digital twin” was published by researchers at Delft University of Technology and NXP Semiconductors. Abstract: "Semiconductor devices are commonly encapsulated with Epoxy-based Moulding Compounds (EMC) to form an electronic package. EMC typically occupies a large volume with... » read more

Scheduling Multi-Model AI Workloads On Heterogeneous MCM Accelerators (UC Irvine)


A technical paper titled “SCAR: Scheduling Multi-Model AI Workloads on Heterogeneous Multi-Chiplet Module Accelerators” was published by researchers at University of California Irvine. Abstract: "Emerging multi-model workloads with heavy models like recent large language models significantly increased the compute and memory demands on hardware. To address such increasing demands, designin... » read more

Compilation Challenges Of Scaling Up Quantum Computing With Superconducting Chiplet Architecture


A technical paper titled “MECH: Multi-Entry Communication Highway for Superconducting Quantum Chiplets” was published by researchers at University of California San Diego, University of California Santa Barbara, and Cisco Quantum Lab. Abstract: "Chiplet architecture is an emerging architecture for quantum computing that could significantly increase qubit resources with its great scalabili... » read more

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