Leveraging In-Package Wireless Technology To Improve The Thermal Behavior Of 2.5D Chiplet-Based SoP

A technical paper titled “REMOTE: Re-thinking Task Mapping on Wireless 2.5D Systems-on-Package for Hotspot Removal” was published by researchers at Swiss Federal Institute of Technology Lausanne (EPFL) and University of Applied Sciences and Arts of Western Switzerland (HES-SO). Abstract Excerpt "In this work, we propose a new task mapping heuristic that leverages in-package wireless t... » read more

A Chiplet-Based Fully Homomorphic Encryption Accelerator

A technical paper titled “CiFHER: A Chiplet-Based FHE Accelerator with a Resizable Structure” was published by researchers at Seoul National University. Abstract: "Fully homomorphic encryption (FHE) is in the spotlight as a definitive solution for privacy, but the high computational overhead of FHE poses a challenge to its practical adoption. Although prior studies have attempted to desig... » read more

Flexible Hybrid Electronics: Future Standards For Next-Gen 5G/mmWave Wearable and Conformal Applications

A technical paper titled “Additively manufactured flexible on-package phased array antennas for 5G/mmWave wearable and conformal digital twin and massive MIMO applications” was published by researchers at Georgia Institute of Technology. Abstract: "This paper thoroughly investigates material characterization, reliability evaluation, fabrication, and assembly processes of additively manufa... » read more

A Performance-Aware Framework For Co-Optimizing Floorplan And Performance Of Chiplet-Based Architecture

A technical paper titled “Floorplet: Performance-aware Floorplan Framework for Chiplet Integration” was published by researchers at Chinese University of Hong Kong and University of California Berkeley. Abstract: "A chiplet is an integrated circuit that encompasses a well-defined subset of an overall system's functionality. In contrast to traditional monolithic system-on-chips (SoCs),... » read more

A Search Framework That Optimizes Hybrid-Device IMC Architectures For DNNs, Using Chiplets

A technical paper titled “HyDe: A Hybrid PCM/FeFET/SRAM Device-search for Optimizing Area and Energy-efficiencies in Analog IMC Platforms” was published by researchers at Yale University. Abstract: "Today, there are a plethora of In-Memory Computing (IMC) devices- SRAMs, PCMs & FeFETs, that emulate convolutions on crossbar-arrays with high throughput. Each IMC device offers its own pr... » read more

Industry 4.0 Paradigms For Chip Workforce Development And Domestic Production: Using Automation And AR/VR

A technical paper titled “From Talent Shortage to Workforce Excellence in the CHIPS Act Era: Harnessing Industry 4.0 Paradigms for a Sustainable Future in Domestic Chip Production” was published by researchers at University of Florida Gainesville, ZEISS Microscopy, and US Partnership for Assured Electronics (USPAE). Abstract: "The CHIPS Act is driving the U.S. towards a self-sustainable f... » read more

A Chiplet-Based FHE Accelerator Design Enabling Scalability And Higher Throughput

A technical paper titled “REED: Chiplet-Based Scalable Hardware Accelerator for Fully Homomorphic Encryption” was published by researchers at Graz University of Technology and Samsung Advanced Institute of Technology. Abstract: "Fully Homomorphic Encryption (FHE) has emerged as a promising technology for processing encrypted data without the need for decryption. Despite its potential, its... » read more

Impact of Clustering Methods On Partitioning Decisions For 3DICs (imec, Université libre de Bruxelles)

A technical paper titled “Impact of gate-level clustering on automated system partitioning of 3D-ICs” was published by researchers at Université libre de Bruxelles and imec. Abstract: "When partitioning gate-level netlists using graphs, it is beneficial to cluster gates to reduce the order of the graph and preserve some characteristics of the circuit that the partitioning might degrade. ... » read more

A Flip-Chip, Co-Packaged With Photodiode, High-speed TIA in 16nm FinFET CMOS

A technical paper titled "A 112-Gb/s —8.2-dBm Sensitivity 4-PAM Linear TIA in 16-nm CMOS With Co-Packaged Photodiodes" was published by researchers at University of Toronto, Alphawave IP, and Huawei Technologies Canada. Abstract: "A flip-chip co-packaged linear transimpedance amplifier (TIA) in 16-nm fin field effect transistor (FinFET) CMOS demonstrating 112-Gb/s four-level pulse-amplitude... » read more

A Chiplet-Based Supercomputer For Generative LLMs That Optimizes Total Cost of Ownership

A technical paper titled "Chiplet Cloud: Building AI Supercomputers for Serving Large Generative Language Models" was published by researchers at University of Washington and University of Sydney. Abstract: "Large language models (LLMs) such as ChatGPT have demonstrated unprecedented capabilities in multiple AI tasks. However, hardware inefficiencies have become a significant factor limiting ... » read more

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