category: Packaging

category: IoT, Security & Automotive

Physics-Based Digital Twin of a Thermally Aged Flip-Chip Package (TU Delft, NXP)
By Technical Paper Link - 29 May, 2024 - Comments: 0

A technical paper titled “Modelling thermomechanical degradation of moulded electronic packages using physics-based digital twin” was published by researchers at Delft University of Technology and NXP Semiconductors. Abstract: "Semiconductor devices are commonly encapsulated with Epoxy-based Moulding Compounds (EMC) to form an electronic package. EMC typically occupies a large volume with... » read more

Scheduling Multi-Model AI Workloads On Heterogeneous MCM Accelerators (UC Irvine)
By Technical Paper Link - 24 May, 2024 - Comments: 0

A technical paper titled “SCAR: Scheduling Multi-Model AI Workloads on Heterogeneous Multi-Chiplet Module Accelerators” was published by researchers at University of California Irvine. Abstract: "Emerging multi-model workloads with heavy models like recent large language models significantly increased the compute and memory demands on hardware. To address such increasing demands, designin... » read more

Compilation Challenges Of Scaling Up Quantum Computing With Superconducting Chiplet Architecture
By Technical Paper Link - 21 May, 2024 - Comments: 0

A technical paper titled “MECH: Multi-Entry Communication Highway for Superconducting Quantum Chiplets” was published by researchers at University of California San Diego, University of California Santa Barbara, and Cisco Quantum Lab. Abstract: "Chiplet architecture is an emerging architecture for quantum computing that could significantly increase qubit resources with its great scalabili... » read more

Chiplet Hardware Security Module To Mitigate Security Vulnerabilities In SiP Systems (Univ. of Florida)
By Technical Paper Link - 09 Apr, 2024 - Comments: 0

A new technical paper titled "Advancing Trustworthiness in System-in-Package: A Novel Root-of-Trust Hardware Security Module for Heterogeneous Integration" was published by researchers at University of Florida (Gainesville). Abstract: "The semiconductor industry has adopted heterogeneous integration (HI), incorporating modular intellectual property (IP) blocks (chiplets) into a unified syst... » read more

U.S. Strategy on Microelectronics Research
By Technical Paper Link - 19 Mar, 2024 - Comments: 0

The U.S. government released a 61 page report titled "National Strategy on Microelectronics Research" by the Subcommittee On Microelectronics Leadership, Committee on Homeland and National Security of the National Science and Technology Council. The report states four goals guiding the agency's efforts in microelectronics research: "Goal 1. Enable and accelerate research advances for futu... » read more

Predicting Warpage in Different Types of IC Stacks At Early Stage Of Package Design
By Technical Paper Link - 15 Mar, 2024 - Comments: 0

A new technical paper titled "Warpage Study by Employing an Advanced Simulation Methodology for Assessing Chip Package Interaction Effects" was published by researchers at Siemens EDA, D2S, and Univ. Grenoble Alpes, CEA, Leti. Abstract: "A physics-based multi-scale simulation methodology that analyses die stress variations generated by package fabrication is employed for warpage study. The ... » read more

Distributed Batteries Within a Heterogeneous 3D IC
By Technical Paper Link - 12 Mar, 2024 - Comments: 0

A new technical paper titled "On-Chip Batteries as Distributed Energy Sources in Heterogeneous 2.5D/3D Integrated Circuits" was published by researchers at University of Florida (Gainesville) and Brookhaven National Lab. Abstract "Energy efficiency in digital systems faces challenges due to the constraints imposed by small-scale transistors. Moreover, the growing demand for portable consum... » read more

UCIe-3D: SiP Architectures With Advanced 3D Packaging With Shrinking Bump Pitches (Intel)
By Technical Paper Link - 12 Mar, 2024 - Comments: 0

A technical paper titled “High-performance, power-efficient three-dimensional system-in-package designs with universal chiplet interconnect express” was published by researchers at Intel. Abstract: "Universal chiplet interconnect express (UCIe) is an open industry standard interconnect for a chiplet ecosystem in which chiplets from multiple suppliers can be packaged together. The UCIe 1.0... » read more

Heterogeneous Integration And Electronics Packaging Manufacturing Roadmap (SEMI & UCLA)
By Technical Paper Link - 09 Feb, 2024 - Comments: 0

A report titled “Manufacturing Roadmap for Heterogeneous Integration and Electronics Packaging (MRHIEP)” was published by researchers at SEMI and the University of California Los Angeles (UCLA)'s Center for Heterogeneous Integration and Performance Scaling (CHIPS), and funded by the National Institute of Standards and Technology (NIST). MRHIEP Goals: "The goal of MRHIEP is to develop an o... » read more

Chiplet Heterogeneity And Advanced Scheduling With Pipelining
By Technical Paper Link - 12 Jan, 2024 - Comments: 0

A technical paper titled “Inter-Layer Scheduling Space Exploration for Multi-model Inference on Heterogeneous Chiplets” was published by researchers at University of California Irvine. Abstract: "To address increasing compute demand from recent multi-model workloads with heavy models like large language models, we propose to deploy heterogeneous chiplet-based multi-chip module (MCM)-based... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy