category: Technical Papers

category: IoT, Security & Automotive

Schottky Barrier Transistors Roadmap (Univ. of Surrey, NaMLab, PGI et al.)
By Technical Paper Link - 17 Nov, 2024 - Comments: 0

A new technical paper titled "Roadmap for Schottky Barrier Transistors" was published by researchers at University of Surrey, NaMLab gGmbH, Forschungszentrum Jülic, Peter Grünberg Institute, et al. Abstract: "In this roadmap we consider the status and challenges of technologies that use the properties of a rectifying metal-semiconductor interface, known as a Schottky barrier, as an asset ... » read more

Ge-Based Multigate SBFETs Operated In An NDR Mode (TU Wien, JKU)
By Technical Paper Link - 15 Nov, 2024 - Comments: 0

A new technical paper titled "Implementation of Negative Differential Resistance-Based Circuits in Multigate Ge Transistors" was published by researchers at TU Wien and JKU (Johannes Kepler University). Abstract: "The co-integration of negative differential resistance (NDR) and Si-based CMOS technology might be a promising concept for multimode devices and circuits with enhanced performance... » read more

Sustainable Hardware Specialization Through Reconfigurable Logic (NUS, Ghent Univ.)
By Technical Paper Link - 15 Nov, 2024 - Comments: 0

A  new technical paper titled "Sustainable Hardware Specialization" was published by researchers at National University of Singapore and Ghent University. "We explore sustainable hardware specialization through reconfigurable logic that has the potential to drastically reduce the environmental footprint compared to a sea of accelerators by amortizing its embodied footprint across multiple a... » read more

Analysis And Design Of Dual-Layer TFTs (Oregon State Univ., Applied Materials)
By Technical Paper Link - 13 Nov, 2024 - Comments: 0

A new technical paper titled "Dual-Layer Thin-Film Transistor Analysis and Design" was published by researchers at Oregon State University and Applied Materials. Abstract "A set of analytical equations is formulated for the analysis and design of a dual-layer thin-film transistor (TFT). For a given TFT structure, in which each channel layer thickness is specified, drain current is calculate... » read more

Distributed Shared Memory That Enlarges Effective Memory Capacity Through Intelligent Tiered DRAM and Storage Management (IIT)
By Technical Paper Link - 13 Nov, 2024 - Comments: 0

A new technical paper titled "MegaMmap: Blurring the Boundary Between Memory and Storage for Data-Intensive Workloads" was published by researchers at Illinois Institute of Technology. "In this work, we propose MegaMmap: a software distributed shared memory (DSM) that enlarges effective memory capacity through intelligent tiered DRAM and storage management. MegaMmap provides workload-aware d... » read more

Dedicated 3D Accelerator Specifically Designed For Emerging Spiking Transformers
By Technical Paper Link - 13 Nov, 2024 - Comments: 0

A new technical paper titled "Spiking Transformer Hardware Accelerators in 3D Integration" was published by researchers at UC Santa Barbara, Georgia Tech and Burapha University. "Recognizing the current lack of dedicated hardware support for spiking transformers, this paper presents the first work on 3D spiking transformer hardware architecture and design methodology. We present an architect... » read more

Systems-in-Package: Authenticated Partial Encryption Protocol For Secure Testing (U. of Florida)
By Technical Paper Link - 12 Nov, 2024 - Comments: 0

A new technical paper titled "GATE-SiP: Enabling Authenticated Encryption Testing in Systems-in-Package" was published by researchers at University of Florida and University of Central Florida. Abstract: "A heterogeneous integrated system in package (SIP) system integrates chiplets outsourced from different vendors into the same substrate for better performance. However, during post-integra... » read more

High-Temperature Processing of Molybdenum Interconnects
By Technical Paper Link - 11 Nov, 2024 - Comments: 0

A technical paper titled "Solving the Annealing of Mo Interconnects for Next-Gen Integrated Circuits" was published by researchers at the National University of Singapore, A*STAR, and imec. Abstract "Recent surge in demand for computational power combined with strict constraints on energy consumption requires persistent increase in the density of transistors and memory cells in integrated ... » read more

Improving Power and Speed in GAA-NS FETs
By Technical Paper Link - 11 Nov, 2024 - Comments: 0

A new technical paper titled "Design Decoupling of Inner-and Outer-Gate Lengths in Nanosheet FETs for Ultimate Scaling" was published by researchers at Belgium Research Center, Huawei Technologies and Global TCAD Solutions. Abstract: "Using a full design-technology-co-optimization (DTCO) methodology, we show the advantages of design decoupling of inner -and outer-gates in gate-all-around ... » read more

Non-Stateful Logic Gates in ReRAM (RWTH Aachen, FZJ)
By Technical Paper Link - 08 Nov, 2024 - Comments: 0

A new technical paper titled "Experimental Verification and Evaluation of Non-Stateful Logic Gates in Resistive RAM" was published by researchers at RWTH Aachen University and Forschungszentrum Jülich GmbH (FZJ). Abstract "Resistively switching, non-volatile memory devices facilitate new logic paradigms by combining storage and processing elements. Several non-stateful concepts such as Sco... » read more

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