category: Security

category: IoT, Security & Automotive

Modeling and Testing Microarchitectural Leakage of CPU Exceptions (Microsoft, Vrije Universiteit Amsterdam)
By Technical Paper Link - 22 Aug, 2023 - Comments: 0

A new technical paper titled "Speculation at Fault: Modeling and Testing Microarchitectural Leakage of CPU Exceptions" was published by researchers at Microsoft and Vrije Universiteit Amsterdam. This paper was included at the recent 32nd USENIX Security Symposium. Abstract: "Microarchitectural leakage models provide effective tools to prevent vulnerabilities such as Spectre and Meltdown vi... » read more

Microarchitectural Side-Channel Attacks And Defenses on NVRAM DIMMs
By Technical Paper Link - 22 Aug, 2023 - Comments: 0

A new technical paper titled "NVLeak: Off-Chip Side-Channel Attacks via Non-Volatile Memory Systems" was published by researchers at UC San Diego, Purdue University, and UT Austin. This paper was included at the recent 32nd USENIX Security Symposium. Abstract: "We study microarchitectural side-channel attacks and defenses on non-volatile RAM (NVRAM) DIMMs. In this study, we first perform r... » read more

Physical Removal Attack On LiDAR Sensors And Mitigation Strategies
By Technical Paper Link - 22 Aug, 2023 - Comments: 0

A technical paper titled "You Can't See Me: Physical Removal Attacks on LiDAR-based Autonomous Vehicles Driving Frameworks" was published by researchers at University of Michigan, University of Florida and the University of Electro-Communications (Japan). This paper was included at the recent 32nd USENIX Security Symposium. Abstract: "Autonomous Vehicles (AVs) increasingly use LiDAR-base... » read more

Formal Processor Model Providing Provably Secure Speculation For The Constant-Time Policy
By Technical Paper Link - 22 Aug, 2023 - Comments: 0

A new technical paper titled "ProSpeCT: Provably Secure Speculation for the Constant-Time Policy" was published by researchers at imec-DistriNet, KU Leuven, CEA, and INRIA. This paper was included at the recent 32nd USENIX Security Symposium. Abstract: "We propose ProSpeCT, a generic formal processor model providing provably secure speculation for the constant-time policy. For constant-tim... » read more

Remote Direct Memory Introspection (Rice, Duke, MIT)
By Technical Paper Link - 22 Aug, 2023 - Comments: 0

A technical paper titled "Remote Direct Memory Introspection" was published by researchers at Rice University, Duke University, and MIT. This paper won a distinguished paper award at the recent 32nd USENIX Security Symposium. Abstract: "Hypervisors have played a critical role in cloud security, but they introduce a large trusted computing base (TCB) and incur a heavy performance tax. As of... » read more

EDA Tool To Detect SW-HW Vulnerabilities Ensuring Data Confidentiality In A RISC-V Architecture
By Technical Paper Link - 18 Aug, 2023 - Comments: 0

A technical paper titled “SoftFlow: Automated HW-SW Confidentiality Verification for Embedded Processors” was published by researchers at RWTH Aachen University, Robert Bosch, and Newcastle University. Abstract: "Despite its ever-increasing impact, security is not considered as a design objective in commercial electronic design automation (EDA) tools. This results in vulnerabilities being... » read more

A Chiplet-Based Fully Homomorphic Encryption Accelerator
By Technical Paper Link - 18 Aug, 2023 - Comments: 0

A technical paper titled “CiFHER: A Chiplet-Based FHE Accelerator with a Resizable Structure” was published by researchers at Seoul National University. Abstract: "Fully homomorphic encryption (FHE) is in the spotlight as a definitive solution for privacy, but the high computational overhead of FHE poses a challenge to its practical adoption. Although prior studies have attempted to desig... » read more

A RISC-V Capability Architecture Orchestrating Compiler, Architecture, And System Designs For Full Memory Safety (Georgia Tech, Arm Research)
By Technical Paper Link - 08 Aug, 2023 - Comments: 0

A technical paper titled “RV-CURE: A RISC-V Capability Architecture for Full Memory Safety” was published by researchers at Georgia Institute of Technology and Arm Research. Abstract: "Despite decades of efforts to resolve, memory safety violations are still persistent and problematic in modern systems. Various defense mechanisms have been proposed, but their deployment in real systems re... » read more

A Chiplet-Based FHE Accelerator Design Enabling Scalability And Higher Throughput
By Technical Paper Link - 07 Aug, 2023 - Comments: 0

A technical paper titled “REED: Chiplet-Based Scalable Hardware Accelerator for Fully Homomorphic Encryption” was published by researchers at Graz University of Technology and Samsung Advanced Institute of Technology. Abstract: "Fully Homomorphic Encryption (FHE) has emerged as a promising technology for processing encrypted data without the need for decryption. Despite its potential, its... » read more

How Attackers Can Read Data From CPU’s Memory By Analyzing Energy Consumption
By Technical Paper Link - 07 Aug, 2023 - Comments: 0

A technical paper titled “Collide+Power: Leaking Inaccessible Data with Software-based Power Side Channels” was published by researchers at Graz University of Technology and CISPA Helmholtz Center for Information Security. Abstract: "Differential Power Analysis (DPA) measures single-bit differences between data values used in computer systems by statistical analysis of power traces. In th... » read more

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