Automating The Detection of Hardware Common Weakness Enumerations In Early Design


A new technical paper titled "Don't CWEAT It: Toward CWE Analysis Techniques in Early Stages of Hardware Design" was published by researchers at NYU, Intel, Duke and University of Calgary. "To help prevent hardware security vulnerabilities from propagating to later design stages where fixes are costly, it is crucial to identify security concerns as early as possible, such as in RTL designs. ... » read more

Decreasing Refresh Latency of Off-the-Shelf DRAM Chips


A new technical paper titled "HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips" was published by researchers at ETH Zürich, TOBB University of Economics and Technology and Galicia Supercomputing Center (CESGA). Abstract "DRAM is the building block of modern main memory systems. DRAM cells must be periodically refreshed to prevent data loss. Refresh oper... » read more

Cybersecurity & FPGA Devices


A technical paper titled "A Survey on FPGA Cybersecurity Design Strategies" is presented by researchers at Université Laval, Canada. Abstract (partial): "This paper presents a critical literature review on the security aspects of field programmable gate array (FPGA) devices. FPGA devices present unique challenges to cybersecurity through their reconfigurable nature. This paper also pays sp... » read more

Implementations of 2D Material-Based Devices For IoT Security


A new research paper titled "Application of 2D Materials in Hardware Security for Internet-of-Things: Progress and Perspective" was published by researchers at National University of Singapore and A*STAR. The paper explores the "implementation of hardware security using 2D materials, for example, true random number generators (TRNGs), physical unclonable functions (PUFs), camouflage, and ant... » read more

Setting The Memory Controller Free From Managing DRAM Maintenance Ops (ETH Zurich)


A new technical paper titled "A Case for Self-Managing DRAM Chips: Improving Performance, Efficiency, Reliability, and Security via Autonomous in-DRAM Maintenance Operations" was published by researchers at ETH Zurich. Abstract: "The rigid interface of current DRAM chips places the memory controller completely in charge of DRAM control. Even DRAM maintenance operations, which are used to en... » read more

Hardware Implementation Of A Random Gumber Generator On A FPGA


A new research paper titled "FPGA Random Number Generator" was published by a researcher at Johns Hopkins University. According to the paper's abstract: "This paper offers a proof-of-concept for creating a verilog-based hardware design that utilizes random measurement and scrambling algorithms to generate 32-bit random synchronously with a single clock cycle on a field-programmable-gate-arr... » read more

New Processor Fuzzing Mechanism


Researchers from Boston University and University of Washington published a technical paper titled "ProcessorFuzz: Guiding Processor Fuzzing using Control and Status Registers." Abstract "As the complexity of modern processors has increased over the years, developing effective verification strategies to identify bugs prior to manufacturing has become critical. Undiscovered micro-architectur... » read more

Evaluation of Automotive HW Trust Anchors Regarding Their Feasibility In Vehicle Architectures


A new technical paper titled "Analysis and Evaluation of Hardware Trust Anchors in the Automotive Domain" was published by researchers at Fraunhofer Institute SIT and CARIAD. Abstract "Automotive architectures get increasingly more complex both regarding internal as well as external connections to offer new services like autonomous driving. This development further broadens the cyberattack ... » read more

Vulnerability of Neural Networks Deployed As Black Boxes Across Accelerated HW Through Electromagnetic Side Channels


This technical paper titled "Can one hear the shape of a neural network?: Snooping the GPU via Magnetic Side Channel" was presented by researchers at Columbia University, Adobe Research and University of Toronto at the 31st USENIX Security Symposium in August 2022. Abstract: "Neural network applications have become popular in both enterprise and personal settings. Network solutions are tune... » read more

ML-Based Framework for Automatically Generating Hardware Trojan Benchmarks


A new technical paper titled "Automatic Hardware Trojan Insertion using Machine Learning" was published by researchers at University of Florida and Stanford University. Abstract (partial): "In this paper, we present MIMIC, a novel AI-guided framework for automatic Trojan insertion, which can create a large population of valid Trojans for a given design by mimicking the properties of a small... » read more

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