Microarchitectural Side-Channel Attacks And Defenses On Non-Volatile RAM


A new technical paper titled “NVLeak: Off-Chip Side-Channel Attacks via Non-Volatile Memory Systems” was written (preprint) by researchers at UC San Diego, UT Austin, and Purdue University.

“We study microarchitectural side-channel attacks and defenses on non-volatile RAM (NVRAM) DIMMs. In this study, we first perform reverse-engineering of NVRAMs as implemented by the Intel Optane DIMM and reveal several of its previously undocumented microarchitectural details: on-DIMM cache structures (NVCache) and wear-leveling policies. Based on these findings, we first develop cross-core and cross-VM covert channels to establish the channel capacity of these shared hardware resources. Then, we devise NVCache-based side channels under the umbrella of NVLeak. We apply NVLeak to a series of attack case studies, including compromising the privacy of databases and key-value storage backed by NVRAM and spying on the execution path of code pages when NVRAM is used as a volatile runtime memory. Our results show that side-channel attacks exploiting NVRAM are practical and defeat previously-proposed defense that only focuses on on-chip hardware resources. To fill this gap in defense, we develop system-level mitigations based on cache partitioning to prevent side-channel leakage from NVCache.”

Find the technical paper here. Prepublication 2023.

Wang, Zixuan, Mohammadkazem Taram, Daniel Moghimi, Steven Swanson, Dean Tullsen, and Jishen Zhao. “NVLeak: Off-Chip Side-Channel Attacks via Non-Volatile Memory Systems.” In USENIX Security Symposium. 2023.

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