category: Test, Measurement & Analytics

category: IoT, Security & Automotive

Scalable Approach For Fabricating Sub-10nm Nanogaps
By Technical Paper Link - 07 Apr, 2025 - Comments: 0

A new technical paper titled "A progressive wafer scale approach for Sub-10 nm nanogap structures" was published by researchers at Seoul National University, Chung-Ang University, Mohammed VI Polytechnic University and Ulsan National Institute of Science and Technology. "We have advanced the atomic layer lithography method into an efficient, scalable approach for fabricating sub-10 nm nanoga... » read more

Defect Analysis and Testing Framework For FOWLP Interconnects
By Technical Paper Link - 24 Mar, 2025 - Comments: 0

A new technical paper titled "Defect Analysis and Built-In-Self-Test for Chiplet Interconnects in Fan-out Wafer-Level Packaging" was published by researchers at Arizona State University. Abstract "Fan-out wafer-level packaging (FOWLP) addresses the demand for higher interconnect densities by offering reduced form factor, improved signal integrity, and enhanced performance. However, FOWLP fa... » read more

Wafer-Level Test Infrastructure for Higher Parallel Wafer Level Testing of SoC
By Technical Paper Link - 03 Mar, 2025 - Comments: 0

A new technical paper titled "Design and Implementation of Test Infrastructure for Higher Parallel Wafer Level Testing of System-on-Chip" was published by researchers at Inha University and Teradyne. Abstract "Semiconductor companies have been striving to reduce their manufacturing costs. High parallelism is a key factor in reducing costs during wafer-level testing. Wafer testing is conduct... » read more

Low-Cost TSV Repair Architecture Specialized for Highly Clustered TSV Faults Within HBM
By Technical Paper Link - 20 Feb, 2025 - Comments: 0

A new technical paper titled "Low Cost TSV Repair Architecture Using Switch-Based Matrix for Highly Clustered Faults" was published by researchers at Yonsei University. Abstract "Through-silicon via (TSV), responsible for inter-layer communication in high-bandwidth memory (HBM), plays a critical role in HBM operation. Therefore, faults occur in TSVs can critically impact the entire chips. H... » read more

Controlling Speckle Contrast Using Existing Lithographic Scanner Knobs to Understand LWR (Samsung, ASML)
By Technical Paper Link - 29 Jan, 2025 - Comments: 0

A new technical paper titled "Controlling Speckle Contrast Using Existing Lithographic Scanner Knobs to Explore the Impact on Line Width Roughness" was published by researchers at Samsung, ASML and Sungkyunkwan University. Abstract "Local critical dimension uniformity (LCDU) or line width roughness (LWR) is increasingly important in argon fluoride (ArF) immersion lithography systems (scanne... » read more

Wafer Bin Map Defect Classification Using Semi-Supervised Learning
By Technical Paper Link - 27 Dec, 2024 - Comments: 0

A new technical paper titled "Semi-Supervised Learning with Wafer-Specific Augmentations for Wafer Defect Classification" was published by researchers at Korea University. Abstract "Semi-supervised learning (SSL) models, which leverage both labeled and unlabeled datasets, have been increasingly applied to classify wafer bin map patterns in semiconductor manufacturing. These models typical... » read more

98 Hardware Security Failure Scenarios (NIST)
By Technical Paper Link - 03 Dec, 2024 - Comments: 0

A new technical paper titled "Hardware Security Failure Scenarios: Potential Hardware Weaknesses" was published by NIST. Abstract "Hardware is often assumed to be robust from a security perspective. However, chips are both created with software and contain complex encodings (e.g., circuit designs and firmware). This leads to bugs, some of which compromise security. This publication evaluate... » read more

Monitor Etch Defects on Dies in the Outer Regions Of The Wafer Using ISR
By Technical Paper Link - 26 Nov, 2024 - Comments: 0

A technical paper titled "Detection of defective chips from nanostructures with a high-aspect ratio using hyperspectral imaging and deep learning" was published by researchers at Samsung Electronics. Abstract: "We have developed an imaging spectroscopic reflectometry (ISR) method based on hyperspectral imaging and deep learning to detect defects in the bottom region of high-aspect-ratio nan... » read more

Visualization of Photoexcited Charges Moving Across the Interface of Si/Ge
By Technical Paper Link - 05 Nov, 2024 - Comments: 0

A technical paper titled "Imaging hot photocarrier transfer across a semiconductor heterojunction with ultrafast electron microscopy" was published by researchers at UC Santa Barbara and UCLA. "In this work, we apply scanning ultrafast electron microscopy to provide a holistic view of photoexcited charge dynamics in a Si/Ge heterojunction. We find that the built-in potential and the band off... » read more

Characterizing Defects Inside Hexagonal Boron Nitride (KAIST, NYU, et al.)
By Technical Paper Link - 23 Oct, 2024 - Comments: 0

A new technical paper titled "Characterizing Defects Inside Hexagonal Boron Nitride Using Random Telegraph Signals in van der Waals 2D Transistors" was published by researchers at KAIST, NYU, Brookhaven National Laboratory, and National Institute for Materials Science. Abstract: "Single-crystal hexagonal boron nitride (hBN) is used extensively in many two-dimensional electronic and quantu... » read more

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