category: Test, Measurement, Analytics tech papers

category: IoT, Security & Automotive

Wafer Bonding Mechanisms Using SiCN Films For Hybrid Bonding Applications In 3D Integration 
By Technical Paper Link - 24 Jun, 2025 - Comments: 0

A new technical paper titled "Material-Mechanistic Interplay in SiCN Wafer Bonding for 3D Integration" was published by researchers at Yokohama National University, TEL, SK hynix, and University of Tsukuba. According to the paper: "Although much research has been conducted on wafer bonding methods compatible with the latest semiconductor manufacturing processes, discussions on the interface... » read more

Domain Adaptation for Image Classification of Defects in Semiconductor Manufacturing (Infineon, U. Padova et al.)
By Technical Paper Link - 21 Jun, 2025 - Comments: 0

A new technical paper titled "Domain Adaptation for Image Classification of Defects in Semiconductor Manufacturing" was published by researchers at Infineon Technologies, University of Padova and University of Bologna. Abstract "In the semiconductor sector, due to high demand but also strong and increasing competition, time to market and quality are key factors in securing significant marke... » read more

A Lightweight Scan Instrumentation For Enhancing The Post-Silicon Test Efficiency in ICs (U. of Florida)
By Technical Paper Link - 31 May, 2025 - Comments: 0

A technical paper titled "Enhancing Test Efficiency through Automated ATPG-Aware Lightweight Scan Instrumentation" was published by researchers at University of Florida. Abstract "Scan-based Design-for-Testability (DFT) measures are prevalent in modern digital integrated circuits to achieve high test quality at low hardware cost. With the advent of 3D heterogeneous integration and chiplet-b... » read more

Overview Of 103 Research Papers On Automatic SEM Image Analysis Algorithms For Semiconductor Defect Inspection (KU Leuven, Imec)
By Technical Paper Link - 20 May, 2025 - Comments: 0

A new technical paper titled "Scanning electron microscopy-based automatic defect inspection for semiconductor manufacturing: a systematic review" was published by researchers at KU Leuven and imec. "We identified, categorized, and discussed automatic defect inspection algorithms that analyze scanning electron microscopy (SEM) images for semiconductor manufacturing (SM). This is a topic of c... » read more

Demonstration Of EUV Scatterometry On A 2D Periodic Interconnect
By Technical Paper Link - 18 May, 2025 - Comments: 0

A new technical paper titled "Coherent EUV scatterometry of 2D periodic structure profiles with mathematically optimal experimental design" was published by researchers at University of Colorado, NIST, Samsung and KMLAbs. Abstract "Extreme ultraviolet (EUV) scatterometry is an increasingly important metrology that can measure critical parameters of periodic nanostructured materials in a fas... » read more

Overview Of Printed And Flexible Electronics: Technology Fundamentals, Design And Practical Applications
By Technical Paper Link - 07 May, 2025 - Comments: 0

A new technical paper titled "Computing with Printed and Flexible Electronics" was published by researchers at Karlsruhe Institute of Technology, Pragmatic Semiconductor Ltd and University of Patras. Abstract "Printed and flexible electronics (PFE) have emerged as the ubiquitous solution for application domains at the extreme edge, where the demands for low manufacturing and operational cos... » read more

Scalable Approach For Fabricating Sub-10nm Nanogaps
By Technical Paper Link - 07 Apr, 2025 - Comments: 0

A new technical paper titled "A progressive wafer scale approach for Sub-10 nm nanogap structures" was published by researchers at Seoul National University, Chung-Ang University, Mohammed VI Polytechnic University and Ulsan National Institute of Science and Technology. "We have advanced the atomic layer lithography method into an efficient, scalable approach for fabricating sub-10 nm nanoga... » read more

Defect Analysis and Testing Framework For FOWLP Interconnects
By Technical Paper Link - 24 Mar, 2025 - Comments: 0

A new technical paper titled "Defect Analysis and Built-In-Self-Test for Chiplet Interconnects in Fan-out Wafer-Level Packaging" was published by researchers at Arizona State University. Abstract "Fan-out wafer-level packaging (FOWLP) addresses the demand for higher interconnect densities by offering reduced form factor, improved signal integrity, and enhanced performance. However, FOWLP fa... » read more

Wafer-Level Test Infrastructure for Higher Parallel Wafer Level Testing of SoC
By Technical Paper Link - 03 Mar, 2025 - Comments: 0

A new technical paper titled "Design and Implementation of Test Infrastructure for Higher Parallel Wafer Level Testing of System-on-Chip" was published by researchers at Inha University and Teradyne. Abstract "Semiconductor companies have been striving to reduce their manufacturing costs. High parallelism is a key factor in reducing costs during wafer-level testing. Wafer testing is conduct... » read more

Low-Cost TSV Repair Architecture Specialized for Highly Clustered TSV Faults Within HBM
By Technical Paper Link - 20 Feb, 2025 - Comments: 0

A new technical paper titled "Low Cost TSV Repair Architecture Using Switch-Based Matrix for Highly Clustered Faults" was published by researchers at Yonsei University. Abstract "Through-silicon via (TSV), responsible for inter-layer communication in high-bandwidth memory (HBM), plays a critical role in HBM operation. Therefore, faults occur in TSVs can critically impact the entire chips. H... » read more

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