Managing EMI in High-Density Integration


The relentless drive for higher performance and increased functional integration has ushered in new challenges for managing electromagnetic interference (EMI) in densely packed mixed-signal environments. Integrating analog, RF, and digital circuits into a single system-on-chip (SoC) or advanced package requires solutions that reduce system size and improve performance. However, this tight in... » read more

3.5D: The Great Compromise


The semiconductor industry is converging on 3.5D as the next best option in advanced packaging, a hybrid approach that includes stacking logic chiplets and bonding them separately to a substrate shared by other components. This assembly model satisfies the need for big increases in performance while sidestepping some of the thorniest issues in heterogeneous integration. It establishes a midd... » read more

Increasing Roles For Robotics In Fabs


Different types of robots with greater precision and mobility are beginning to be deployed in semiconductor manufacturing, where they are proving both reliable and cost-efficient. Static robots have been used for years inside of fabs, but they now are being supplemented by collaborative robots (cobots), autonomous mobile robots (AMRs), and autonomous humanoid robots to meet growing and widen... » read more

Building Smarter, Better Fabs


Battling labor shortages, faster ramp rates, and data overload, the process of designing and building greenfield fabs requires a combination of tech tools, failing earlier approaches and superior planning from day one. The complexity and scale of semiconductor fabs is skyrocketing as is the capital cost. Chipmakers are looking to ramp multibillion dollar fabs faster despite the hurdles of la... » read more

Why Small Fab And Assembly Houses Are Thriving


High-volume products get more than their fair share of attention in the semiconductor world, but most chips don't fit into that category. While a few huge fabs and offshore assembly and test (OSAT) houses process enormous volumes of chips, small fabs and packaging lines serve for lower volumes, specialized technology, and prototyping. “There are companies that run literally one lot of 25 w... » read more

Reasons To Know IGZO


Interest in monolithic 3D integration is driven by both compute-in-memory applications and a more general need for increased circuit density. Compute-in-memory architectures seek to reduce the power requirements of machine learning workloads, which are dominated by the movement of data between memory and logic components. Even in conventional architectures, though, placing high-density, high-ba... » read more

Key Technologies To Extend EUV To 14 Angstroms


The top three foundries plan to implement high-NA EUV lithography as early as 2025 for the 18 angstrom generation, but the replacement of single exposure high-NA (0.55) over double patterning with standard EUV (NA = 0.33) depends on whether it provides better results at a reasonable cost per wafer. So far, 2024 has been a banner year for high-numerical aperture EUV lithography. Intel Foundry... » read more

Legacy Process Nodes Going Strong


While all eyes tend to focus on the leading-edge silicon nodes, many mature nodes continue to enjoy robust manufacturing demand. Successive nodes stopped reducing die cost at around the 20nm node. “In the finFET era of processes, esoteric process requirements necessary to move technology forward with each generation have added significant cost and complexity,” explained Andrew Appleby, p... » read more

Precision Patterning Options Emerge For Advanced Packaging


The chip industry is ratcheting up investments in advanced packaging as it strives to keep pace with demands for increased functionality and higher performance, including novel patterning technologies that can reduce costs and speed time to market. Success in advanced packages is partly dependent on effectively managing the interconnectivity between the chips, which requires increasingly pre... » read more

New Interconnect Metals Need New Dielectrics


Just as circuit metallization must evolve to manage resistance as features shrink, so must the dielectric half of the interconnect stack. For quite some time, manufacturers have needed a dielectric constant (k) less than 4, which is the value for SiO2, but they have struggled to find materials that combine a low dielectric constant with mechanical and chemical stability. In work presented at... » read more

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