E-beam’s Role Grows For Detecting IC Defects


The perpetual march toward smaller features, coupled with growing demand for better reliability over longer chip lifetimes, has elevated inspection from a relatively obscure but necessary technology into one of the most critical tools in fab and packaging houses. For years, inspection had been framed as a battle between e-beam and optical microscopy. Increasingly, though, other types of insp... » read more

Keeping IC Packages Cool


Placing multiple chips into a package side-by-side can alleviate thermal issues, but as companies dive further into die stacking and denser packaging to boost performance and reduce power, they are wrestling with a whole new set of heat-related issues. The shift to advanced packaging enables chipmakers to meet demands for increasing bandwidth, clock speeds, and power density for high perform... » read more

Removing Barriers For End-To-End Analytics


Parties are coming together, generating guidelines for sharing data from IC design and manufacturing through end of life, setting the stage for true end-to-end analytics. While the promise of big data analytics is well understood, data sharing through the semiconductor supply chain has been stymied by an inability to link together data sources throughout the lifecycle of a chip, package, or ... » read more

The Race To Zero Defects In Auto ICs


Assembly houses are fine-tuning their methodologies and processes for automotive ICs, optimizing everything from inspection and metrology to data management in order to prevent escapes and reduce the number of costly returns. Today, assembly defects account for between 12% and 15% of semiconductor customer returns in the automotive chip market. As component counts in vehicles climb from the ... » read more

Bridging IC Design, Manufacturing, And In-Field Reliability


Experts at the Table: Semiconductor Engineering sat down to talk about silicon lifecycle management and how that can potentially glue together design, manufacturing, and devices in the field, with Prashant Goteti, principal engineer at Intel; Rob Aitken, R&D fellow at Arm; Zoe Conroy, principal hardware engineer at Cisco; Subhasish Mitra, professor of electrical engineering and computer sci... » read more

Hidden Impacts Of Software Updates


Over-the-air updates can reduce obsolescence over longer chip and system lifetimes, but those updates also can impact reliability, performance, and affect how various resources such as memory and various processing elements are used. The connected world is very familiar with over-the-air (OTA) updates in smart phones and computers, where the software stack — firmware, operating systems, dr... » read more

Where And When End-to-End Analytics Works


With data exploding across all manufacturing steps, the promise of leveraging it from fab to field is beginning to pay off. Engineers are beginning to connect device data across manufacturing and test steps, making it possible to more easily achieve yield and quality goals at lower cost. The key is knowing which process knob will increase yield, which failures can be detected earlier, and wh... » read more

How AI/ML Improves Fab Operations


Chip shortages are forcing fabs and OSATs to maximize capacity and assess how much benefit AI and machine learning can provide. This is particularly important in light of the growth projections by market analysts. The chip manufacturing industry is expected to double in size over the next five years, and collective improvements in factories, AI databases, and tools will be essential for doub... » read more

Lots Of Data, But Uncertainty About What To Do With It


Experts at the Table: Semiconductor Engineering sat down to talk about silicon lifecycle management in heterogeneous designs, where sensors produce a flood of data, with Prashant Goteti, principal engineer at Intel; Rob Aitken, R&D fellow at Arm; Zoe Conroy, principal hardware engineer at Cisco; Subhasish Mitra, professor of electrical engineering and computer science at Stanford University... » read more

Strategies For Faster Yield Ramps On 5nm Chips


Leading chipmakers TSMC and Samsung are producing 5nm devices in high volume production and TSMC is forging ahead with plans for first 3nm silicon by year end. But to meet such aggressive targets, engineers must identify defects and ramp yield faster than before. Getting a handle on EUV stochastic defects — non-repeating patterning defects such as microbridges, broken lines, or missing con... » read more

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