category: Top Stories

category: IoT, Security & Automotive

Delivering On Power During HPC Test
By Anne Meixner - 09 Jul, 2024 - Comments: 0

The industry’s insatiable need for power in high-performance computing (HPC) is creating problems for test cells, which need to deliver very high currents at very consistent voltage levels through the power delivery network (PDN). In response, ATE, wafer probe, and contactor vendors are introducing some innovative approaches and test procedures that can ensure robust power delivery to ATE pro... » read more

Digital Twins Find Their Footing In IC Manufacturing
By Laura Peters - 09 Jul, 2024 - Comments: 0

Momentum is building for digital twins in semiconductor manufacturing, tying together the various processes and steps to improve efficiency and quality, and to enable more flexibility in the fab and assembly house. The movement toward digital twins opens up a slew of opportunities, from building and equipping new fabs faster to speeding yield ramps by reducing the number of silicon-based tes... » read more

X-ray Inspection Becoming Essential In Advanced Packaging
By Gregory Haley - 09 Jul, 2024 - Comments: 0

X-ray technology is moving into the mainstream of chip manufacturing as complex assemblies and advanced packaging make it increasingly difficult to ensure these devices will work as expected throughout their lifecycles. A single defect in a chiplet or interconnect can transform a complex advanced package into expensive scrap, and the risk only increases as the chip industry shifts from homog... » read more

What’s Missing In Test
By Anne Meixner - 19 Jun, 2024 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss how functional test content is brought up at first silicon, and the balance between ATE and system-level testing, with Klaus-Dieter Hilliges, V93000 platform extension manager at Advantest Europe; Robert Cavagnaro, fellow in the Design Engineering Group at Intel (responsible for manufacturing and test strategy of data center... » read more

Power-Aware Revolution In Automated Test For ICs
By Gregory Haley - 11 Jun, 2024 - Comments: 0

As semiconductor devices advance in complexity and sensitivity to power fluctuations, the integration of power-aware automatic test pattern generation (ATPG) is becoming indispensable for yield and the overall functionality of a chip. Unlike traditional ATPG, which generates test patterns solely to ensure device functionality, power-aware ATPG takes it a step further by meticulously consider... » read more

Speeding Up Metrology At Advanced Nodes
By Gregory Haley - 11 Jun, 2024 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to talk metrology at the most advanced nodes and the impact of using different substrates, with Frank Chen, director of applications and product management at Bruker Nano Surfaces & Metrology; John Hoffman, computer vision engineering manager at Nordson Test & Measurement; and Jiangtao Hu, senior technology director at Onto Inn... » read more

3D Metrology Meets Its Match In 3D Chips And Packages
By Laura Peters - 11 Jun, 2024 - Comments: 0

The pace of innovation in 3D device structures and packages is accelerating rapidly, driving the need for precise measurement and control of feature height to ensure these devices are reliable and perform as expected throughout their lifetimes. Expansion along the z axis is already well underway. One need look no further than the staircase-like 3D NAND stacks that rise like skyscrapers to p... » read more

Using Predictive Maintenance To Boost IC Manufacturing Efficiency
By Laura Peters - 14 May, 2024 - Comments: 0

Predicting exactly how and when a process tool is going to fail is a complex task, but it's getting a tad easier with the rollout of smart sensors, standard interfaces, and advanced data analytics. The potential benefits of predictive maintenance are enormous. Higher tool uptime correlates with greater fab efficiency and lower operating costs, so engineers are pursuing multiple routes to boo... » read more

The Future Of Fault Coverage In Chips
By Gregory Haley - 14 May, 2024 - Comments: 0

Heterogeneous integration and sophisticated packaging are making chips more difficult to test, necessitating more versatile and efficient testing methods to minimize the time and cost it takes for each test insertion. In the past, test costs typically were limited to about 2% of the total cost of a chip. That cost has been rising in recent years, and with chiplets, advanced packaging, and mo... » read more

Doing More At Functional Test
By Anne Meixner - 14 May, 2024 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss the increasing importance of functional test, especially in high-performance computing, with Klaus-Dieter Hilliges, V93000 platform extension manager at Advantest Europe; Robert Cavagnaro, fellow in the Design Engineering Group at Intel (responsible for manufacturing and test strategy of data center products); Nitza Basoco, tec... » read more

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