Multicore Debug Evolves To The System-Level


The proliferation and expansion of multicore architectures is making debug much more difficult and time-consuming, which in turn is increasing demand for more comprehensive system-level tools and approaches. Multicore/multiprocessor designs are the most complex devices to debug. More interactions and interdependencies between cores mean more things possibly can go wrong. In fact, so many pro... » read more

Forward And Backward Compatibility In IC Designs


Future-proofing of designs is becoming more difficult due to the accelerating pace of innovation in architectures, end markets, and technologies such as AI and machine learning. Traditional approaches for maintaining market share and analyzing what should be in the next rev of a product are falling by the wayside. They are being replaced by best-guesses about market trends and a need to bala... » read more

Silo Busting In The Design Flow


An increasing number of dependencies in system design are forcing companies, people, tools, and flows to become more collaborative. Design and EDA companies must adapt to this new reality because it has become impossible for anyone to do it all by themselves. Moreover, what happens in manufacturing and packaging needs to be considered up front, and what gets designed in the design phase may ... » read more

Using AI And Bugs To Find Other Bugs


Debug is starting to be rethought and retooled as chips become more complex and more tightly integrated into packages or other systems, particularly in safety- and mission-critical applications where life expectancy is significantly longer. Today, the predominant bug-finding approaches use the ubiquitous constrained random/coverage driven verification technology, or formal verification techn... » read more

Brute-Force Analysis Not Keeping Up With IC Complexity


Much of the current design and verification flow was built on brute force analysis, a simple and direct approach. But that approach rarely scales, and as designs become larger and the number of interdependencies increases, ensuring the design always operates within spec is becoming a monumental task. Unless design teams want to keep adding increasing amounts of margin, they have to locate th... » read more

Speeding Up AI With Vector Instructions


A search is underway across the industry to find the best way to speed up machine learning applications, and optimizing hardware for vector instructions is gaining traction as a key element in that effort. Vector instructions are a class of instructions that enable parallel processing of data sets. An entire array of integers or floating point numbers is processed in a single operation, elim... » read more

A Renaissance For Semiconductors


Major shifts in semiconductors and end markets are driving what some are calling a renaissance in technology, but navigating this new, multi-faceted set of requirements may cause some structural changes for the chip industry as it becomes more difficult for a single company to do everything. For the past decade, the mobile phone industry has been the dominant driver for the semiconductor eco... » read more

Using Verification Data More Effectively


Verification is producing so much data from complex designs that engineering teams need to decide what to keep, how long to keep it, and what they can learn from that data for future projects. Files range from hundreds of megabytes to hundreds of gigabytes, depending on the type of verification task, but the real value may not be obvious unless AI/machine learning algorithms are applied to a... » read more

Is Hardware-Assisted Verification Avoidable?


Emulation is emerging as the tool of choice for complex and large designs, but companies that swap from simulation to emulation increasingly recognize this is not an easy transition. It requires money, time, and effort, and even then not everyone gets it right. Still, there are significant benefits to moving from simulation to emulation, providing these systems can be utilized efficiently en... » read more

RISC-V: Will There Be Other Open-Source Cores?


Part 3: Semiconductor Engineering sat down to discuss the business and technology landscape for RISC-V with Zdenek Prikryl, CTO of Codasip; Helena Handschuh, a Rambus Security Technologies fellow; Louie De Luna, director of marketing at Aldec; Shubhodeep Roy Choudhury, CEO of Valtrix Systems; and Bipul Talukdar, North America director of applications engineering at SmartDV. What follows are exc... » read more

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