A Renaissance For Semiconductors

New horizontal technologies and vertical markets are fueling the opportunities for massive innovation throughout an expanding ecosystem.


Major shifts in semiconductors and end markets are driving what some are calling a renaissance in technology, but navigating this new, multi-faceted set of requirements may cause some structural changes for the chip industry as it becomes more difficult for a single company to do everything.

For the past decade, the mobile phone industry has been the dominant driver for the semiconductor ecosystem, from EDA and IP to foundries. That industry has hit a plateau in growth, but new drivers are emerging in verticals such as automotive, medical and industrial, and in horizontals such as artificial intelligence, More than Moore, and in managing growing constraints on power and thermal.

This kind of turmoil looks as if it will be good for the entire semiconductor ecosystem, and innovation is at the highest level in recent memory. “If the ESD Alliance Market Statistics Service (MSS) Q2 report is an indicator, EDA is growing despite the smart phone industry plateauing,” says Bob Smith, executive director of ESD Alliance. “Chip companies are clearly designing new end-user products. According to the report, CAE and IC Physical design are up substantially, while PCB is down slightly. Longer term, CAE and IC Physical Design have been generally trending up, and that infers new chip design activity is proceeding.”

The industry now has multiple drivers. “Until 10 years ago, you would find single big inflection points,” says Michal Siwinski, corporate vice president for market and business development at Cadence. “It would be datacoms, and then it would be mobile, but that has evolved. Over the last five years it started to become multi-faceted. A lot of the push for innovation used to come primarily from mobile, because mobile was pushing the envelope of things harder than anyone else. They still are, but in addition the hyperscalers are pushing other verticals that depend on large data center infrastructure or adding intelligence to all kind of compute, be it in consumer products, be it in industrial, be it in automotive, be it in aerospace. It’s a good problem but it’s almost too many drivers.”

One example of divergence can be seen between mobile and high-performance compute (HPC). “The end of Dennard Scaling impacted both groups but the responses of each were somewhat different,” says Thom Gregorich, director of business development for Carl ZEISS SMT. “HPC continued to pursue more advanced fab nodes, implemented multi-core designs, and supported those processors with arrays of conventional DRAM packages. Mobile caught-up to HPC in the pursuit of advanced fab nodes and subsequently dominated leading-edge fab business due to their larger purchasing power. They also implemented multi-core designs with sophisticated POP DRAM solutions to address the physical constraints of mobile. The ending of Moore’s Law hit HPC first, and to some extent resulted in the development of HBM DRAM and 2.5D packages to circumvent the DRAM performance wall. At the same time, the POP technology portfolio continued to provide mobile with sufficient bandwidth.”

Mobile certainly is not standing still. “Mobile is becoming a lot more advanced,” says Vic Kulkarni, vice president and chief strategist at Ansys. “Now the technology is being embedded into everything we do, from 5G handhelds to base stations, and it will end up in many other markets. This generates a lot of mobile data, which will require massive compute.”

New horizontals
Horizontals cut across all end markets and require attention throughout the ecosystem. In the past horizontals were typified by the von Neumann computing architecture, implemented in a monolithic CMOS technology, and verification. Power got added to that later. In the past few years, new horizontals are becoming increasingly important, including artificial intelligence, security and More-than-Moore.

“What’s really driving the next push is data,” says Michael Sanie, vice president for marketing and strategy of the Design Group at Synopsys. “There is so much data, and that has two big impacts. First are the devices that move the data – the network. It could be any of the data networking chips or broadband or 5G – anything that moves data around. Latency is a challenge, and bandwidth and capacity are limited. Second, we need more processing for that data – compute. There are two big parts of that, high performance computing, and AI chips. How do you make sense out of the data sets? Networking and compute are the next drivers.”

New compute architectures are emerging. “Artificial intelligence, machine learning, deep learning is pervasive,” says Cadence’s Siwinski. “We talk about pervasive intelligence and that’s not just an interesting play on words, it is precisely because we’ve seen aspects of machine learning and deep learning getting inserted across every single vertical market. There is so much data and compute explosion across every vertical and every single piece of electronics that supports it, that you almost have to add machine learning to basically be smarter and more efficient with that compute, otherwise you get a bit overwhelmed because there is so much of it.”

AI is turning up everywhere. “The increasing use of AI across a variety of markets is one of the most exciting technological advancements in a generation,” says Chet Babla, vice president for the Automotive and IoT Line of Business at Arm. “We are now seeing smart asthma inhalers that use AI to provide enhanced respiratory care, and smart contact lenses that use microelectronics and a tiny display to share critical information with the wearer.”

Even within artificial intelligence there are multiple facets to the problem. “From an SoC architecture standpoint, think of a 2 x 2 matrix where you have data center versus edge on one side,” says Kurt Shuler, vice president of marketing at Arteris IP. “People may argue about where the dividing line is, but you could think of it as stuff that runs off a battery versus stuff that has to be plugged in. The other side is artificial intelligence, and there are two aspects to that. One is training the neural network, and the other is using that neural network in the real world — inference. So you have this 2 x 2 matrix of data center versus edge, and training versus inference.”

Another new horizontal is security. “Cybersecurity and anti-piracy are quickly becoming huge challenges,” says ESD Alliance’s Smith. “These impact hardware designers, software and software IP developers, and the entire semiconductor manufacturing ecosystem.”

Security issues are also pervasive. “We’re getting to a point where almost every chip company — not necessarily just aerospace and defense, but now automotive — is adopting the thought process of ‘trust nothing and no one,'” says Synopsys’ Sanie. “We need to provide methodology, IP, design technology, 3D-ICs that meets the PPA needs, but also have known security and reliability, not only for today, but for the next 5 years or 15 years, depending on the industry. This means that silicon lifecycle management becomes a huge challenge for customers. It not only impacts design and manufacturing, but extends into the field. Can you look at the device and predict performance challenges or security gaps throughout the lifecycle of an SoC?”

Without safety and security, technological advances may be limited. “Arm is trying to accelerate autonomous decision-making with safety capability across automotive and industrial applications,” says Arm’s Babla. “Autonomy has the potential to improve every aspect of our lives, but only if built on a safe and secure computing foundation.”

Moore’s Law used to be a generic driver that cut across most vertical markets, especially for markets that could take advantage of extra area, lower power and could benefit from the most advanced nodes. “That driver continues,” says Siwinski. “Everybody said that we would not be able to get past certain nodes, but here we are kicking strong at 7nm, 5nm, 3nm, and exploring 2nm. About 10 years ago, power became the number one threshold. Power is extremely important, but now it is power and thermal intertwined throughout the systems. That is a horizontal vector.”

Moore’s Law is no longer the only path forward. “The industry is going beyond Moore, also known as More than Moore,” says Ansys’ Kulkarni. “We have moved into the era of data-centric, which is enabling new verticals (see figure 1). Everything gets connected in a bigger and bigger way. And that’s why it’s a renaissance, because we see growth of semiconductors, growth of electronics, and growth within everything that feeds these, such as photonics, mechanical, thermal for managing heat. All these effects come in as you go toward the new world, the data-centric world of Moore’s Law.”

Fig 1. Semiconductor Industry Mega Trends. Source: Ansys

Changes such as these impact many areas. “People are re-looking at design architectures, and this is where a lot of the differentiation is between the chipmakers, especially on the HPC side and AI chip market,” says Sanie. “They’re finding really cool ways to architect their chips to leverage what’s available in terms of silicon geometry, and they’re getting good clock speed. But they also are addressing things with better methodology, better technology that gets them the PPA, the performance, and power optimizations they need. And what’s upcoming is heavy usage of multi-chip 3D-IC types of architectures, and eventually we’ll get to a point of heterogeneous integration of chips.”

“People are expanding the divide and conquer approach by dividing the system into multiple chiplets,” says Kulkarni. “Then you can have disparate functions on the same kind of a subsystem, you can have stacked die, interposer, 2.5D structures. A recent example is the intelligent vision sensor that is a 3D-IC stack with CMOS sensor arrays on top of an AI chip, so a lot of machine learning and AI is built into the chip to make intelligent decisions for not only for autonomous but also for mobile.”

The deployment of chiplets will be gated by the availability of scalable, cost-effective solutions. “Chiplets are one of several post-Moore package technologies that are in development, including micro-TSVs, micro-solder connections, copper-fusion interconnects, high-density organic substrates, and high-density fan-out packages,” says Carl ZEISS’ Gregorich. “Several prominent semiconductor companies have predicted that bumped interconnect pitch will scale by over 100:1 during the next 10 years. This paradigm-shift will impact both HPC and mobile, and we expect that each segment will optimize for their specific needs. For example, chiplets and TSVs will be utilized by both segments. High-density substrate packages and high-density fan-out packages will be optimized for each segment. In both segments, successful package solutions will have the following characteristics: (1) they will have acceptable cost/benefit ratios and be scalable in capacity; (2) they will not adversely affect manufacturing yields or field reliability.”

The emergence of chiplets requires changes throughout the design flow. “Several aspects in chip design, such as control of individual functional blocks, and most importantly the design of interfaces between wafers, between dies or between packages, need specific design,” says Paul Lindner, executive technology director for EV Group. “IDMs and foundries, which own the building blocks, including the interfaces for 3D integration, are taking full advantage of these new integration trends and are preparing for them accordingly. At the same time, heterogeneous integration opens up business opportunities on the packaging side, where OSATs are well positioned.”

Emerging verticals
Technologies initially developed in one vertical are now being used to expand others. “A workload that has evolved from the smart phone industry, and which is driving a change in computing, is autonomous decision-making,” says Babla. “We experience autonomous systems every day, such as when our smart phone unlocks itself having decided our face meets the visual criteria, and automation capability is now becoming more pervasive across both vehicles and factory environments. Developers designing autonomous systems require technology that meets the relevant safety standards, is scalable to address a range of workloads and processing capabilities, as well as energy-efficient and secure.”

Others agree. “One obvious market driver is the move toward autonomous driving,” says Smith. “This is due in large measure to the rapid pace of innovation in the automotive market and recent mandates in numerous geographies pushing for full electrification.”

This can influence the direction of IP developers. “If you look at our slides from a decade ago, there were 20 application processor vendors and digital baseband modem vendors,” says Arteris’ Shuler. “We focused our business on that market and reasoned that if we met their needs, we would meet the needs of everyone. When you look at our slides today, there are five of them because they consolidate over time. Today, we consider the requirements for automotive. We believe that if we meet the AI requirements that they have, we meet the requirements for anybody, or almost anybody in that market. So someone who is doing robotics or industrial will have their needs met if we meet the needs of automotive.”

An often talked about vertical is the IoT. “IoT is very interesting because IoT is a byproduct of recent advances,” says Sanie. “Data is not centralized anymore. It’s getting pushed to the edge. And that creates this weird continuum that data is centralized but also getting pushed to the edge. At the same time, compute was also centralized, but compute itself is also getting pushed towards the edge. It’s creating this compute continuum between Cloud and servers and edge devices and back and forth, and 5G suddenly becomes this big ether between these continuums.”

Even COVID is influencing the verticals. “COVID has changed the focus in the market and there are new problem formulations getting developed,” says Siwinski. “This disruption, and disruptions in general, create either opportunities or chaos. A lot of the time for technology, they create opportunities, and COVID is no exception.”

COVID has created the need for more distributed systems. “That direction was already in progress, but COVID has definitely accelerated that move,” says Sanie. “If you look at the networking and compute companies, their challenges, and their requests to us have not stopped because of COVID. In fact, one could say that they’ve accelerated.”

More collaboration
One impact of the new horizontals and verticals is that everyone in the ecosystem is stretched thin. Problems have become much broader, requiring increasing levels of cooperation between companies.

IP suppliers and EDA tooling have always had a very close connection to foundries,” says Siwinski. “Around 10nm, or a little before, the nature of that collaboration started to shift. Before, it used to be innovation done primarily on the foundry side, and then EDA tooling and IP adjusting to that new reality. With the newer nodes, collaboration has blossomed into a much closer partnership. R&D organizations are working much more closely with the foundries, not just on support, but on mutual innovation. It has enabled faster innovation.”

There are more system issues, as well. “We look at what’s beyond electronics, what’s beyond semiconductors, what’s beyond systems,” says Kulkarni. “That includes mechanical, CFD (computational fluid dynamics), and some photonics. EDA, IP, the whole ecosystem, packaging people who are often considered as an afterthought, now have to come together because decisions made in one affect the other areas as well. Stronger collaboration will be required. For example, what you do when power impacts timing — so-called voltage timing issues? Then heat becomes a problem, so you need mechanical stress and warpage analysis and thermal analysis.”

And within design teams, groups that used to work separately now have to come together. “It’s not like the old days where you would make a chip and then say, ‘Given this chip, what can I do in the software?'” says Shuler. “Instead it has become, given what my software has to do, what do I need to do at a system level? Here’s the new processing elements I need to create, here’s the new data flow that I need to create to keep them fed, here’s where I need to put memories to make sure that I can do the gathering functions for the thousands of processing elements that all need data at the same time. Whether it’s automotive or AI, even though we’re dealing with a horizontal capability, we have to be able to understand higher up in the value chain what they are trying to do.”

It also demands collaboration between EDA tools. “Methodology becomes a bigger piece, not only for better power or performance, but methodology that go beyond SoC optimization and looks at system level optimization,” says Sanie. “At that point, we have to look at different verticals. How do you do power management for an automotive chip, versus a high-performance computing chip, versus a mobile chip? They’re all different. And how you do power management, performance management, even silicon lifecycle management? Each is different, and therefore we have system-level methodologies that are more targeted at a vertical.”

Siwinski agrees. “A lot of the leading customers are pulling us into these conversations, and we get asked to basically invent a brand new flow, a brand new methodology to support these super-aggressive innovation goals. Then other companies use those methodologies and they become the new normal and the new best practices. The methodologies to support things evolve. It used to be about specific point technologies because the methodology was step by step. Now complexity is driving much closer native automations between the various technologies at the engine levels.”

The industry also is witnessing greater levels of cooperation between EDA companies, or between business units within the larger organizations.

New horizontals and new verticals are driving innovation across the entire ecosystem today, something that has never happened in the past. This is going to create challenges and opportunities and will require many companies to decide where they will be the experts and where they will partner. We have seen examples of this already, but we should expect to see many more in the future.

“We’re just starting to scratch the surface of what is going to start coming,” says Siwinski. “I’m not saying this is going to be like The Renaissance, where there was a biological challenge that created disruption and created centuries of different innovation. Granted, two centuries ago it was a very different world, but at the end of the day you’re going to see one technology feeding many diverse opportunities. Consider firefighters with the pandemic. It becomes more difficult for them to do their job, but why not take this technology and create a brand-new sub-market for autonomous firefighting drones.”

Confusion Grows Over Packaging And Scaling
The number of options is increasing, but tooling and methodologies haven’t caught up.
New Architectures, Much Faster Chips
Massive innovation to drive orders of magnitude improvements in performance.
Momentum Builds For Advanced Packaging
Increasing density in more dimensions with faster time to market.
Deals That Change The Chip Industry
More acquisitions are on the horizon.


Diego Fenner says:

Thank you for your insights.
here are indeed so many new things we can do.

S.R.S. says:

Any thoughts regarding Silicon on Insulator as a way to expand beyond Moore?

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