New Math: 1+1=1?


From the standpoint of place and route, synthesis, and even some pieces of the hardware verification, the cost of chips even at advanced nodes hasn’t budged. It’s now possible to create a chip at 28nm with roughly the same budget as a 40nm chip, and inside many companies that’s what the hardware engineering manager sees. Look across the entire SoC design chain, however, and the picture... » read more

Experts At The Table: Verification Nightmares


By Ed Sperling Low-Power Engineering sat down with Shabtay Matalon, ESL marketing manager in Mentor Graphics’ Design Creation Division; Bill Neifert, CTO at Carbon Design Systems; Terrill Moore, CEO of MCCI Corp., and Frank Schirrmeister, director of product marketing for system-level solutions at Synopsys. What follows are excerpts of that conversation. LPE: Where does power fit in? N... » read more

New Forces For Consolidation


For the past five-plus decades, the overriding effect of Moore’s Law was to put more circuits on a single piece of silicon. While that’s still the case, the addition of multiple cores since 90nm also has meant more functions can be added to that chip, which creates a whole new business equation for makers of complex devices like smart phones. Instead of creating individual chips, a single... » read more

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