category: Design & Verification

category: IoT, Security & Automotive

It’s Time To Get Your University In Sync With Zynq
By Aldec - 25 Aug, 2016 - Comments: 0

By Zach Nelson It’s time for universities to say goodbye to their outdated FPGA boards and introduce the Xilinx Zynq chip. The chip is a device which combines an FPGA fabric with a processing unit. The chip is very similar to other FPGA devices, but it does have a few key advantages and features that can enhance your designs and increase its capabilities. What can Zynq do? The Zynq ... » read more

To Emulate Or Prototype?
By Krzysztof Szczur - 28 Jul, 2016 - Comments: 0

FPGA Prototyping is more challenging than emulation. Yet for the time invested in prototype setup, developers are rewarded with a validation platform that is capable of running orders of magnitude faster than emulation. Emulation also has  benefits that appeal especially to design verification engineers. Aside from the completely automated compilation and setup flow, it offers robust debugg... » read more

The UVM Configuration Database
By Henry Chan - 30 Jun, 2016 - Comments: 0

When I want to wear a certain clothing item, I take out it of the closet. When I go shopping, I add those clothes it to my closet and there are now new items for me to pick out in the future. A database works much the same way, a collection of information that is stored and accessed on demand. Take the UVM configuration database for example. It basically acts as a repository so that when the... » read more

The Hardest Part Of DO-254 Is…
By Louie De Luna - 26 May, 2016 - Comments: 0

The hardest part of DO-254 is not the requirements. It’s not the design. It’s not the verification. We just wrapped up this year’s 3-day DO-254 Practitioner’s Course, and each year I learn something new. In this year’s training we had attendees from major aerospace companies including Curtiss Wright, Rolls Royce, Sierra Nevada Corporation, Thales and Woodward. It’s always a pleas... » read more

UVM Register Layer: The Structure
By Henry Chan - 28 Apr, 2016 - Comments: 0

I don’t know about you, but I am looking forward to the day where we won’t even have to go to the doctor’s office for an exam. Instead, we will all have scanners in our homes that will transmit full digital models to our doctors who can then poke, prod, and examine us remotely. This is essentially what the UVM register layer allows and does. The UVM register layer acts similarly by mod... » read more

Why I See C In SCE-MI
By Jacek Majkowski - 24 Mar, 2016 - Comments: 0

The two questions I hear most often while doing presentations about SCE-MI transaction based emulation are, “Can we have coffee break?” and “Why do we need a thin C layer between two SystemVerilog tops”? You a probably reading this during a coffee break, so let’s jump to second question. It refers to this diagram showing how to connect a SystemVerilog testbench (usually UVM) with D... » read more

UVM: It’s Organized And Systematic
By Henry Chan - 25 Feb, 2016 - Comments: 0

One of the reasons I like using UVM is its tendency toward an organized structure and uniformity. Some may find it annoying to adhere to such a strict format in UVM, but I think it’s a good way to keep the basics of UVM engrained in your brain. You always want a good foundation and development of strong fundamentals in any endeavor. Verification is no different and UVM hammers the fundamental... » read more

Reprogrammable, Reprogrammable, Reprogrammable
By Aldec - 28 Jan, 2016 - Comments: 0

By Alex Grove I like FPGAs. My first experience with an FPGA was my university final year project where I demonstrated BIST with four Xilinx© 3000 devices; this was before FPGAs had JTAG built in. Filling up these devices with ViewDraw schematics required many hours in front of a terminal. Fast track to today’s advances such as Xilinx UltraScale and Vivado HLx, and I hope you would agree ... » read more

U.V.M. Spells Relief
By Henry Chan - 22 Dec, 2015 - Comments: 0

Verification can be a challenging endeavor. As designs grow in size and complexity, engineers are having difficulty confirming their designs behave properly. This is where UVM may provide some relief. UVM aims to deliver an easier and more flexible way of creating robust test environments so that you can verify those difficult designs effortlessly. So what is UVM? UVM is a verification meth... » read more

The Problem With CDCs
By Louie De Luna - 24 Nov, 2015 - Comments: 0

Part of the Planning Process in DO-254 is knowing the appropriate FPGA tools and capabilities that you need and intend to use for your FPGA design. Particularly if your FPGA device operates with multiple asynchronous clocks which necessitates using advanced verification techniques targeting anomalies related to clock domain crossings (CDCs). Typical electronic design automation (EDA) tools f... » read more

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