RISC-V Verification: The 5 Levels Of Simulation-Based Processor Hardware DV

By Lee Moore - 29 Jul, 2021 - Comments: 1

By Lee Moore and Simon Davidmann The RISC-V open standard ISA (Instruction Set Architecture) offers developers the opportunity to configure the features and functions of a custom processor to uniquely address their target end application needs and requirements. RISC-V has a modular structure with many standard instruction extensions for additional dedicated hardware features such as Floating... » read more

Adding Value To Open-Source RISC-V Cores With Verification

By Lee Moore - 22 Apr, 2021 - Comments: 0

By Steve Richmond (Silicon Labs), Mike Thompson (OpenHW Group), and Lee Moore (Imperas Software) Modern SoC verification has matured to the point that some are suggesting the use of the word ‘prototype’ when referring to the first silicon samples is now unnecessary. This is due in part to the commercial EDA industry, which has provided the innovation and tools used throughout the design... » read more

The Lost Art Of Processor Verification

By Kevin McDermott - 04 Jan, 2021 - Comments: 0

As we celebrate over 50 years of microprocessors, the industry has embraced every generation of silicon process technology with architectural innovation plus new design methods that have supported innovations in almost every market segment. The interest around RISC-V is opening up increased activity around new approaches to optimize designs for the next generation of devices across multiple mar... » read more

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category: Lost Art Of Processor Verification

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RISC-V Verification: The 5 Levels Of Simulation-Based Processor Hardware DV

Adding Value To Open-Source RISC-V Cores With Verification

The Lost Art Of Processor Verification