The Lost Art Of Processor Verification

Using SoC methodologies for RISC-V processor DV.


As we celebrate over 50 years of microprocessors, the industry has embraced every generation of silicon process technology with architectural innovation plus new design methods that have supported innovations in almost every market segment. The interest around RISC-V is opening up increased activity around new approaches to optimize designs for the next generation of devices across multiple market segments. Without the one-size-fits all constraints of traditional embedded processor IP, system designers are again looking at tradeoffs and flexibility to find new optimized solutions.

At one time, almost every major semiconductor supplier had a proprietary microprocessor architecture. However, over time the customer’s and/or end user’s investment in software helped drive consolidation in many markets around a few standard ISA’s. The ecosystem and software reuse became the key requirement for any roadmap plans. Innovation was focused around the peripherals and dedicated hardware functionality which was marketed as either general-purpose MCUs or as application/market specialist devices (ASSPs). As the growth in complexity expanded, the design verification (DV) task become more specialized and advanced. The state of the industry today is that first pass silicon success is no longer exceptional but routine and expected with confidence.

While the results of the latest DV methodologies are impressive, another often quoted reference is that DV accounts for 50% to 80% of the costs for a new SoC design. The fundamental assumption of current SoC verification plans is that the ‘known-good’ processor IP cores delivered by an expert processor team do not need further verification, and so are not included in the test plan (or time/cost estimated above). Also, as almost all IP is single sourced, compatibility and compliance are a given. The SoC verification effort is therefore targeted towards the interfaces and other block level testing around the interfaces to the processor core IP, and the adoption of SystemVerilog for test and verification has become the de facto industry standard for UVM based SoC verification.

The Open Standard instruction set architecture (ISA) of RISC-V enables a new level of flexibility for SoC developers, with axes of choice including: 1) sourcing options (commercial providers, open-source, or self-build), 2) architectural options (optional configurations of instruction extensions plus custom instructions and registers) and 3) microarchitectural implementations (e.g. for pipeline, FPU, etc.). This allows system developers the degrees of freedom needed to fine tune the processor for the exact requirements. Therefore, all RISC-V based SoC developments will have to address some level of processor verification.

During a panel session at DVCon (March 2020, San Jose) on Processor DV, this comment by EDA industry pioneer Jim Hogan, of Vista Ventures, captured the current views on the state of reliability of RISC-V cores: “I’m sure none of you would use RISC-V IP and expect first silicon correct without first completing your own due diligence and incoming inspection DV.”

As SoC teams are now addressing the complexities of RISC-V DV they have a natural starting point with SystemVerilog and UVM that are central to the SoC verification methodologies. An SoC verification plan has 4 components: coverage metrics, tests to run, a target to test (DUT) and a reference model to compare against.

The Imperas RISC-V reference model has been adopted by many customers, IP providers and industry groups and has the unique ability to support encapsulation within a UVM SystemVerilog environment. It has been used by:

  • The RISC-V International Task Group to develop and validate the reference compliance test suite.
  • Customers such as Mellanox (NVIDIA), developing implementation and/or custom instructions.
  • Valtrix test generator for RISC-V ISA including privileged mode and vector extensions.
  • The OpenHW group verification plan for the CORE-V open source cores.
  • The Google ISG (Instruction Stream Generator) open source project under Chips Alliance group for RISC-V testing.
  • Companies such as Seagate using the free riscvOVPsim for processor verification.
  • Encapsulated within SystemVerilog and verified within the Cadence, Mentor, Synopsys and Metrics environments.

The Imperas SystemVerilog UVM step-and-compare analysis offers a number of advantages to the processor DV task, as it allows the side-by-side verification of the processor RTL directly compared with reference model. In contrast to static log file analysis this allows both an interactive debug experience and also is more efficient as unnecessary simulation cycles are avoided after an issue is found. Also, utilizing SystemVerilog test benches with an automated approach permits techniques such as continuous integration and regression testing.

While some aspects of processor verification are understood in a general approach some of the biggest impacts of the innovation developing around RISC-V is the collaboration of system developers, hardware & software designers, and DV engineers as the implications across all aspects of the design are important considerations as design options are reviewed. DV may will be the last task before a successful tape-out but increasingly the DV plans and implications are being considered from product inception and throughout the cross functional development team. To paraphrase a famous U.S. advertising commercial – two engineers were reviewing a RISC-V project verification plan when the system design engineer asked, how do you spell “reliability” and the DV engineer answered “I-M-P-E-R-A-S”.

* “Reliability: the degree to which the result of a measurement, calculation, or specification can be depended on to be accurate.” Source credit: Oxford English Dictionary

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