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Coverage-Directed Test Selection Method for Automatic Test Biasing During Simulation-Based Verification


New research paper titled "Supervised Learning for Coverage-Directed Test Selection in Simulation-Based Verification" from researchers at University of Bristol and Infineon Technologies. Abstract: "Constrained random test generation is one the most widely adopted methods for generating stimuli for simulation-based verification. Randomness leads to test diversity, but tests tend to repeate... » read more

Automated Conversion Of Xilinx Vivado Projects To ALINT-PRO


Aldec's ALINT-PRO design verification solution performs static RTL and design constraints code analysis to uncover critical design issues early in the design cycle. The product helps FPGA developers rise to the challenge of designing large FPGA designs and multiprocessor system on chip devices that include high-capacity and high-performance FPGA hardware. The solution supports running rule c... » read more

Rocky Road To Designing Chips In The Cloud


EDA is moving to the cloud in fits and starts as tool vendors sort out complex financial models and tradeoffs while recognizing a potentially big new opportunity to provide unlimited processing capacity using a pay-as-you-go approach. By all accounts, a tremendous amount of tire-kicking is happening now as EDA vendors and users delve into the how and why of moving to the cloud for chip desig... » read more

The Lost Art Of Processor Verification


As we celebrate over 50 years of microprocessors, the industry has embraced every generation of silicon process technology with architectural innovation plus new design methods that have supported innovations in almost every market segment. The interest around RISC-V is opening up increased activity around new approaches to optimize designs for the next generation of devices across multiple mar... » read more