Customized On-Chip Process Monitors

The sensitivity of digital circuits to process variations is continuously increasing with scaling in MOSFET devices. The effect of process variations has a substantial impact on the power, performance, and reliability of products. These process variations can be local or across the chip or wafer-to-wafer, or even lot-to-lot. These process variations need to be observed and analyzed in order to ... » read more

Inside The Hybrid Memory Cube

The memory bandwidth requirements for today’s high-performance computing applications and next-generation networking applications have increased beyond what conventional memory architectures can provide. For example in a typical 400G networking application, packet buffer bandwidth requirement could be as high as 2,000 Gb/s. Achieving this level of bandwidth using the latest DDR4 memory te... » read more

Speeding Up Timing Constraint Creation, Refinement And Validation

We are dealing with designs integrating many features and working with cutting-edge process technologies. Design methodologies and the design and process complexities can be overwhelming. To leverage the advancements in EDA tools and to achieve optimal power, performance and area results while overcoming design complexities, it is important to have a qualitative timing constraint file that c... » read more

From Specification To Chip: A Holistic Design Approach

Chip design is getting more and more challenging in terms of power, performance, area and IP integration. At the same time, competition and time-to-market are forcing much tighter schedules. The traditional ASIC design approach taken by OEMs is to handle the majority of front-end design in-house, and then hand off either register-transfer level (RTL) code or a netlist to an outside vendor, who ... » read more

Hybrid Memory Cube – Ready For Prime Time

With the release this week of Hybrid Memory Cube (HMC) 2.0, designers can get their hands on mature, standards-based IP that can be used to significantly scale the performance of servers and data centers. HMC offers bandwidths up to 320 GB/s – 12X that of standard memory solutions like DDR4 – while consuming significantly less power. These benefits are too significant to ignore for ASIC, So... » read more

A New Reuse Paradigm To Take 2.5D Packaging Technology Mainstream

With all of the recent product implementations and demonstrations of the technical viability of 2.5D technology, there is a lot of excitement around its potential. However, as with any new technology, there are concerns with cost and risk that limit mainstream adoption. Cost reduction and risk mitigation require some level of volume production, and therein lies a classic Catch-22. Is there a wa... » read more

Evaluation Platforms Key To Complex IP Integration

Just because a chip is complex to build doesn’t mean it has to take a long time. Runaway complexity in SoC and ASIC design is forcing chip companies to consider different methodologies and approaches that could actually simplify and speed up the whole process. The first step in this process was commercial IP, and its growing popularity attests to the fact that chipmakers are looking for... » read more

Software Design Moves Virtual Prototyping Into The Mainstream

With the high level of integration of CPUs, GPUs, and DSPs in today’s System-on-Chip (SoC) and ASIC devices, software is becoming a primary driver of system innovation. This, along with the increasing pressure to reduce system development time, makes it critical to get a working hardware prototype into the hands of the various software teams as quickly as possible. Traditional prototyping met... » read more