A New Reuse Paradigm To Take 2.5D Packaging Technology Mainstream

Die reuse only improves costs when the dies are actually re-used.


With all of the recent product implementations and demonstrations of the technical viability of 2.5D technology, there is a lot of excitement around its potential. However, as with any new technology, there are concerns with cost and risk that limit mainstream adoption. Cost reduction and risk mitigation require some level of volume production, and therein lies a classic Catch-22. Is there a way to develop a more compelling cost model that would justify the risk?

One approach to consider is die reuse in multiple 2.5D-packaged products. This approach requires die to be developed with I/Os appropriate for die-to-die signaling over a silicon interposer for signals not going outside the package. It treats dies similarly to today’s standard chips and the silicon interposer as the PCB. With this approach, dies with various standard functions, such as CPU subsystems, memories, high-speed serial peripherals, sensors, and other standard functions could be mixed and matched on the interposer for various applications. The trick is deciding how to determine what functionality constitutes a “standard” die that has a high likelihood of reuse.

One would naturally assume that the functionality found in current standard parts would apply, but there are some interesting differences in 2.5D packaging that might drive the decisions another way. First, die-to-die I/Os are very small and can have as low as a 40-micron pitch. The signaling traces across the interposers also have a fine pitch, typically 1-5 microns, and the capacitive loading is much smaller than a PCB trace. All of these characteristics change the thinking about I/O planning. There’s less motivation to limit I/O count, so communications paths can be wider and still operate near the core clock speeds without special signal conditioning. For example, a CPU die can be mated with a SDRAM memory die without using a high-speed PHY, which potentially reduces silicon area and power consumption. Data paths between logic functions on separate dies can be as wide as the internal interconnect, and can almost be thought of as an extension of the interconnect. Of course, the logical interfaces must be standardized in order for the die reuse paradigm to work. These would be dependent on the decisions made about functional partitioning and would need to take a long-range outlook for how the dies might be assembled in future products.

With more flexibility in how to interface to the dies, other considerations may come into play. The obvious one is to keep like technologies on separate dies. For example, memory technologies such as FLASH and SDRAM should be on separate dies from logic and analog, just as they are in standard parts. Due to the necessary inclusion of a PHY, high-speed serial peripherals might be implemented in a less aggressive, higher-voltage logic process just to improve cost. With a standardized die-to-die I/O electrical design, all these dissimilar technologies can be integrated into a single package.

The die reuse approach only improves cost when the dies are actually re-used, which means someone has to have the motivation to invest in them from the start. A possible candidate would be a smart phone developer that also wants to go into wearable electronics, because many of the same technologies in processing, memories, wireless communications, sensors, displays and more are common to both. If all the silicon in a cell phone was initially developed to have 2.5D packaging technology, then a subset might later be used to implement a smart watch or fitness bracelet. The smart phone would drive volume and therefore reduce cost and risk for the dies used in the wearable products. A large amount of planning and coordination would need to go into the partitioning of functionality into the various dies and packages. There also may be tradeoffs involving the use of over-spec’d parts in the less complex devices just to take advantage of existing dies. Additionally, 2.5D packaging provides an overall area reduction benefit that would align well with the form factor requirements of wearables.

So, a new paradigm for reuse, from IP in chips and chips on boards, to IP in dies and dies in packages, could lead the way to earlier adoption of 2.5D packaging in emerging mainstream products.

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